Hitachi, Ltd.

Other

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hatachi Ltd

Hitachi, Ind.

Yoichi Tamaki

Takeo Shiba

Akihisa Uchida

Takahide Ikeda

Toshihiko Takakura

Masao Kawamura

Toshiyuki Kikuchi

Kazuhiro Ohnishi

Takashi Uchino

Takashi Kobayashi

Hiromi Shimamoto

Kazuhiko Sagara

Tokuo Kure

Katsumi Ogiue

Takashi Hashimoto

Tohru Nakamura

Hideo Miura

Hisayuki Higuchi

Shigeo Kuroda

Mikinori Kawaji

Daisuke Okada

Asao Nishimura

Hiroyuki Ohta

Katsuyoshi Washio

Hiroo Masuda

Takahiro Onai

Takayuki Iwasaki

Akira Sato

Takahiro Kumauchi

Chiyoshi Kamada

Kiyoji Ikeda

Kousuke Tsuji

Satoshi Yamamoto

Hiroshi Kikuchi

Masao Kondo

Norio Hasegawa

Takeshi Shimano

Toshiyuki Mine

Hirotaka Nishizawa

Eiichi Murakami

Shinji Okazaki

Kenji Maio

Masanobu Miyao

Noriyuki Homma

Tetsuya Hayashida

Shigeharu Kimura

Hiromichi Enami

Satoru Isomura

Osamu Kasahara

Masato Hamamoto

Akitoshi Ishizaka

Taiga Arai

Masahiko Ogirima

Akira Shintani

Takeshi Doi

Shinji Nakajima

Seiichi Isomae

Fujiaki Nose

Michiyoshi Maki

Hideaki Nonami

Toru Koizumi

Toru Nakamura

Kaoru Ohgaya

Kunihiko Watanabe

Daisuke Okaka

Masayoshi Saitoh

A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipolar transistors. A deep trench isolation surrounds a group of or the whole of the plurality of unit bipolar transistors that are connected in parallel, for a plurality of desired bipolar transistor that require thermal stability.

Semiconductor device

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Semiconductor device and process of producing the same

The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrateto form a bipolar transistor having a large current capacity.

Semiconductor device and method for fabricating the same

A semiconductor device improved in reliability is disclosed. The semiconductor device comprises a semiconductor chip, a sealing member which seals the semiconductor chip with resin, a tub having a chip bonding surface for bonding with the chip and a back surface located on the side opposite to the chip bonding surface and exposed to a surface of the sealing member, plural inner leads electrically connected respectively to bonding pads on the semiconductor chip through wires such as gold wires, and plural outer leads integrally connected respectively to the inner leads and projecting to the exterior of the sealing member, wherein surfaces of the tub and the plural inner and outer leads are all coated with palladium plating. In the case where a heat radiation member is attached to the back surface of the tub, the palladium plating does not melt during solder reflow for example, so that the heat radiation member can be prevented from falling off and hence it is possible to improve the reliability of a QFP as the semiconductor device.

The number of design processes for fabricating semiconductor devices can be reduced by parallel connection of a plurality of unit bipolar transistors Qu that are completely electrically isolated from each other in a semiconductor layer of an SOI substrate to form a bipolar transistor having a large current capacity.

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

A photo semiconductor integrated circuit device has a photodiode portion and amplifier portion, each portion having a buried layer. The impurity concentration and/or depth of the buried layer for the photodiode portion is lower than that of the buried layer for the amplifier portion. As a result, the frequency band width is widened.

Photo semiconductor integrated circuit device and optical recording reproducing apparatus

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

A method of manufacturing a bipolar transistor having an improved polysilicon emitter is disclosed. More specifically, hydrogen terminations or OH group terminations adhered (bonded) to an emitter-forming region are eliminated by a heat treatment in an inert gas atmosphere before forming emitter polysilicon. Subsequently, an amorphous silicon film for forming an emitter polysilicon is formed at a low temperature.

Method of manufacturing semiconductor integrated circuit device

Semiconductor device having conducting structure

A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

Method of manufacturing a BIMIS

A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

Process for producing a bipolar device

Bipolar device and production thereof

Growing community of inventors

Kokubunji, Japan

Yoichi Tamaki