Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Hitachi, Vlsi Eng. Corp.

Yoichi Sato

Masao Mizukami

Satoshi Shinagawa

Toshiyuki Ookuma

Yukio Nakano

Takahiko Kozaki

Akira Ito

Masami Hasegawa

Yasushi Shimono

Takatoshi Tamura

Yoshio Iioka

Tosiyuki Ohkuma

Masayuki Miyasaka

Write column selection MOSFETs of memory cells MC are coupled with, for example, the earth potential of the circuit. Write column selection signals supplied to these MOSFETs are formed selectively according to the column selection address signal and the write data. Thereby the write column selection MOSFETs of the memory cells MC function as a substantial write means. That is, the write column selection signal lines are used as the data lines at the same time.

Multiplexed multi-write port semiconductor memory

A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

Semiconductor integrated circuit

A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

Semiconductor storage device

A multi-port memory device has a memory cell array including one or more memory blocks each of which has a plurality of memory cells arranged in rows and columns, and a plurality of dummy cells, with one dummy cell being provided for each row of memory cells in each of the memory blocks so that the dummy cells are connected with associated ones of the word lines extending in the row direction. The dummy cells are further connected with dummy cell bit lines extending in the column direction. Sense amplifiers are connected to receive outputs of those memory cells in the memory cell array which are selected in a memory cell selection operation and outputs of those dummy cells among the plurality of dummy cells which are selected in the memory cell selection operation for amplifying differences between the selected memory cell outputs and the selected dummy cell outputs. Precharging and shielding arrangements are also provided for improved operation.

Multi-port memory device having precharged bit lines

A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Complementary signal transmission circuit with impedance matching

A static random access memory (RAM) includes a data set circuit (DSC) coupled to pairs of load elements of memory cells to test the connection between a pair of load elements and a pair of memory nodes of each of the memory cells. The data set circuit responds to predetermined control signals and data to be set to the memory cells and supplies the predetermined voltage corresponding to such data to the pair of load elements. If the pair of load elements and the memory nodes of a memory cell are properly coupled, data of the memory cell will be inverted. Therefore, if the data of a memory cell is not inverted during the test, it can be quickly determined that a disconnection fault exists at that memory cell location.

Semiconductor memory with a circuit for testing characteristics of

Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are prechanged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory. The memory array is implemented in a semiconductor storage device, such as a static RAM, which is characterized as operating either as a one-port or two-port system and wherein it, furthermore, employs a write amplifier circuit arrangement and a sense amplifier arrangement, such as of the single-ended differential type, wherein the write and sense amplifier arrangements can be disposed either on separate common data lines or on a single common data line.

A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted outpout to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

High speed sensor system using a level shift circuit

A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted output to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are precharged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory.

Semiconductor storage device with common data line structure

A semiconductor memory device is provided which includes a plurality of word line drivers and logic decoding circuitry coupled to the inputs of the word line drivers. In large memory arrays, the word line driver circuits can place large capacitive loads on the output of the logic decoding circuit because the word line driver transistors must be relatively large. This large load on the logic decoding circuitry adversely effects the operating speed of the memory. Accordingly, to reduce this load, a switching arrangement is provided between the output of the logic decoding circuitry and the word line drivers. This switching arrangement can be controlled to respectively connect the output of the logic decoding circuit to the word line drivers based on control output signals of a pre-decoder. Reset MOSFETs can also be provided to prevent the inputs of the word line drivers from floating.

Semiconductor memory device with first and second word line drivers

Plural pairs of complementary data lines coupled with plural memory cells are precharged to a positive source voltage level and a pair of common complementary data lines corresponding to the plural pairs of complementary data lines are precharged to ground potential. In synchronism with selection of a word line, a pair of the plural pairs of complementary data lines and the common complementary data lines are coupled through a switch circuit. A sense amplifier coupled with the common complementary data lines is supplied with a voltage composed of a voltage of approximately half the voltage value of the positive supply voltage and a readout voltage from the memory cell superposed thereon. Thus, after the precharging operation, there is no need for an equalizing operation before a word line is selected. Therefore, high-speed reading can be achieved.

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Iruma, Japan

Yoichi Sato