Sony Corporation

Sony Computer Entertainment Inc.

International Business Machines Corporation

Yoichi Nishino

Sang Hoo Dhong

Osamu Nakamura

Brian King Flachs

Takashi Kohashi

Jonathan James DeMent

Yuuki Matsumura

Atsushi Hayashi

Akiyuki Hatakeyama

Gilles Gervais

Douglas Hooker Bradley

Hiroshi Yoshihara

Shunichi Soma

Taichi Niki

Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.

Methods and apparatus for managing defective processors through power gating

Methods and apparatus provide for powering up a static random access memory (SRAM); interrogating at least some contents of the SRAM resulting from power up; and using the contents as at least a basis of a random number.

Methods and apparatus for random number generation

A data processing apparatus and data processing method enabling a camera generating image data to be identified easily with a high reliability, which identify if a predetermined image generating apparatus having distinctive variations in light receiving intensity of individual light receiving elements and generating image data based on light receiving results of the plurality of light receiving elements generated the first image data to be identified, wherein a correlation detector detects correlation between first image data and second image data for reference generated using a predetermined image generating apparatus and a CPU identifies if the first image data was generated using an image generating apparatus based on that correlation.

Data processing apparatus and associated method of identifying an image data source by detecting variations in strength of different light receiving elements

A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

System and method for sorting processors based on thermal design point

Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.

Methods and apparatus for producing an IC identification number

A digital watermark embedding processor and digital watermark embedding-processing method set the lowest-common-multiple picture size of the sizes of an unconverted picture and a converted picture when embedding digital watermarks on certain data having a possibility of format conversion and set, for the lowest-common-multiple picture size, the values of the digital watermarks in the converted picture. Based on the set values, digital watermarks for the unconverted picture are set and are embedded in the picture. In this construction, even when a watermark-embedded picture is processed for conversion, it is ensured that accurate detection from the converted picture of watermarks can be performed.

Digital watermark embedding processor, digital watermark detecting processor, digital watermark embedding-processing method, digital watermark detecting-processing method, and program storage medium and program used therewith

An input/output circuit wherein a plurality of data lines are provided with a serial/parallel conversion means common to all, so that the circuit is enabled to consume less power and draw a reduced instantaneous current in its operation and be fabricated in an integrated circuit form.

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Tokyo, Japan

Yoichi Nishino