Seiko Instruments Inc

Sii Semiconductor Corporation

Ablic Inc.

Yoichi Mimuro

Toshihiko Omi

Kotaro Watanabe

Shinjiro Kato

Yukimasa Minami

Tetsuo Shioura

A semiconductor device includes a substrate; a laminate which is formed on one main surface side of the substrate, and includes an aluminum alloy wiring and an insulating film surrounding the aluminum alloy wiring; and a silicon nitride film covering the laminate, in which the silicon nitride film and the insulating film have an opening portion, through which the silicon nitride film and the insulating film, formed at a position overlapped with a bonding portion of the aluminum alloy wiring, and a deposition made of a residue caused by reverse sputtering, which contains silicon and nitrogen, adheres to a portion exposed from the opening portion of a surface of the aluminum alloy wiring, to form a film.

Semiconductor device and method of manufacturing the same

Provided is an integrated circuit having a LOCOS-drain type MOS transistor mounted thereon in which, even in the case of poor pattern formation, a withstand voltage is not lowered and a poor withstand voltage does not result. A drain oxide film thicker than a gate oxide film is formed on an active region on a drain side of the LOCOS-drain type MOS transistor, to thereby prevent the withstand voltage of the MOS transistor from being lowered even if the gate electrode reaches the active region on the drain side.

Semiconductor device

Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.

Flip-chip mounted semiconductor device

A plurality of line image sensor ICsare formed to be arranged in X, Y directions with gaps therebetween on a semiconductor substrate. The gaps between the line image sensor ICsbecome scribe linesX,Y. A pattern of dummy interconnectsis formed in a region where a short sideS of an arbitrary line image sensor ICis opposed to a short sideS of another line image sensor ICadjacent to the arbitrary line image sensor ICin the X direction in a region where the scribe lineY is formed. When a material gas is generated by plasma CVD, the material gas is uniformly deposited not only on the line image sensor ICs, but also on the dummy interconnects. Consequently, a protective film with a uniform thickness can be formed on the line image sensor ICs

Photoelectric conversion device and method of producing the same, and method of producing line image sensor IC

Provided is a photoelectric conversion device including: a semiconductor substrate () of a first conductivity type; a photoelectric conversion region () of a second conductivity type which is located in the semiconductor substrate (), the second conductivity type being opposite to the first conductivity type; and a buried layer () of the first conductivity type which is formed in an inner portion of the semiconductor substrate () to cover a lower side of the photoelectric conversion region (), the buried layer () including a higher impurity concentration than the semiconductor substrate ().

Photoelectric conversion device, image sensor, and method of manufacturing a photoelectric conversion device

A Vss-side off transistor is often used in an electrostatic breakdown prevention circuit having an NMOS transistor. In such a circuit, the state of connection of the transistor ensures that off-leak current has a significant influence on the standby current, which is particularly noticeable when the circuit is used in a semiconductor device running at low power consumption. In such case, since the threshold voltage of a MOS transistor forming the semiconductor device is made as low as possible, the sub-threshold leak current in the electrostatic breakdown prevention circuit is large. To prevent this, the NMOS transistor forming the electrostatic breakdown prevention circuit is formed with a P type gate electrode for the purpose of increasing its threshold voltage by about 1.1 V as compared with that if the gate electrode of the NMOS transistor were to have an N type gate electrode.

Growing community of inventors

Chiba, Japan

Yoichi Mimuro