Renesas Electronics Corporation

Nippon Telegraph and Telephone Corporation

Trio Kabushiki Kaisha

Yoichi Maeda

Takayuki Suzuki

Jun Matsushima

Hideshi Maeno

Hiroki Wada

Koichi Saito

Kiyomi Kumozaki

Youichi Fukada

Yoshitaka Taki

Susumu Abe

Yoshinori Nishida

A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor deviceincludes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Semiconductor device and method of controlling self-diagnosis

An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

Semiconductor device and diagnostic method therefor

There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

Semiconductor device and diagnosis method thereof

A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

Semiconductor device and scan test method including writing and reading test data

In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Semiconductor device, electronic control system and method for evaluating electronic control system

A semiconductor device () according to the present invention includes a circuit to be tested () having a scan chain, and a first test control device () and a second test control device () that perform a scan test of the circuit to be tested by using the scan chain. The second test control device () performs a second scan test of the circuit to be tested (), the circuit to be tested () gives the first test control device () an instruction to perform a first scan test after the second scan test is performed, and the first test control device () performs a first scan test of the circuit to be tested () in response to an instruction from the circuit to be tested ().

Semiconductor device and diagnostic test method for both single-point and latent faults using first and second scan tests

A semiconductor device includes a first circuit and a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit. A pattern-generator control circuit controls each of the plurality of pattern generators such that the pattern generator starts to operate when a control signal is at a first level and the pattern generator stops operating when the control signal is not at the first level. A pattern compressor compresses a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators. A pattern-compressor control circuit controls the pattern compressor. A self-diagnosis control circuit is connected to the pattern-generator control circuit and the pattern-compressor control circuit and controls the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators due to changing the control signals to selectively stop the pattern generators in a predetermined manner.

Semiconductor device

A power-on self-test circuit and a pattern generation circuit are provided. The power-on self-test circuit includes a selection circuit and a comparator circuit. The selection circuit selects, instead of an external pin group corresponding to a test access port, an output of the pattern generation circuit when a self-diagnosis execution signal is asserted and supplies a test pattern generated by the pattern generation circuit to a built-in self-test circuit. The comparator circuit compares a test result of a circuit-under-test with an expected value. By asserting the self-diagnosis execution signal in this manner, the semiconductor integrated circuit mounted on a user system executes BIST.

Semiconductor integrated circuit and method for designing the same

A transmitting apparatus arranges data in matrix, calculates error correction codes in the data's column direction, arranges the calculated error correction codes in matrix having the same number of columns as the data, attaches number information corresponding to a row number to each row having data or error correction code, encapsulates, into each packet, each row having number information and data or error correction code, plus error detection code detecting one or more bit errors at least in the number information and the data or error correction code in the packet, and transmits the packet. Receiving apparatus discards received packets having detected errors using the error detection code in each packet, checks packet losses according to number information, and restores lost data using the error correction codes. An error correction method compensates for packet losses and bit errors in a packet, realizing efficient transmission with less delay by simple configuration.

Error correction method and apparatus

A speaker system comprising a speaker unit, a drone cone driven by the speaker unit; and a removable weight loaded on the front of the drone cone which can be exchanged from the front of the drone cone.

Growing community of inventors

Tokyo, Japan

Yoichi Maeda