Fujitsu Corporation

Yoichi Koyanagi

Takeshi Horie

Osamu Shiraki

Toshiyuki Shimizu

Hiroaki Ishihata

Kenichi Hayashi

A parallel computer including a plurality of processing elements, each of processing elements comprising a flag address holding unit for temporarily holding an address of a send complete flag of a direct remote write message when the direct remote write message is sent to another processing element, and a flag update unit for exclusively updating a flag represented by the address held in the flag address holding unit when data indicated by the direct remote write message has been sent.

Parallel computer which verifies direct data transmission between local

An overflow control unit stores, in a FIFO buffer, data generated by a processor. The overflow control unit sets a predetermined flag, upon detecting that a FIFO buffer is full or nearly full. The overflow control unit stores, in a saving buffer, data sent from the processor, while the flag is set. Thereafter, the overflow control unit notifies the processor, by an interrupt, of an effect that an available capacity of the FIFO buffer rises above a predetermined threshold. Upon receiving an interrupt, the processor transfers to the FIFO buffer data saved in the saving buffer. Upon a completion of transferring to the FIFO buffer all data saved in the saving buffer, the processor resets the flag. This allows the overflow control unit to again store in the FIFO buffer, data sent from the processor. The overflow control unit also monitors the volume of data stored in the saving buffer, and notifies the processor, by an interrupt, of an effect that the saving buffer is full. Upon receiving an interrupt, the processor expands an available capacity of the saving buffer.

Queue control apparatus including memory to save data received when

A storage region formed of a nonvolatile storage device is divided into two blocks; block `0` and block `1`. In a process for writing data, the magic Nos. of the blocks `0` and `1` are checked. On condition that both the magic Nos. have a correct value, the sequential Nos. of the blocks `0` and `1` are compared so as to select the block whose sequential No. has a smaller value. The data to-be-written is written into the selected block. Subsequently, a value obtained by adding '1' to the sequential No. of the unselected block is written as the sequential No. of the selected block. Lastly, the magic No. is written into the selected block. On the other hand, in a process for reading data, the magic Nos. of the blocks `0` and `1` are checked. On condition that both the magic Nos. have the correct value, the block whose sequential No. has a larger value is selected, and the data to-be-read is read out of the selected block. According to the present invention, even in a case where the power of the storage device has turned off during the data write process and where the data write has not been completed, data before the write process remain. Even when the data are the set values or the likes of, for example, a computer system, the remaining data can be used for avoiding the state of the system incapable of starting.

Storage apparatus having a nonvolatile storage device capable of

When the processor writes a command data string into an address of the command entry area, a corresponding command is created by a bus interface. If an address output by the processor corresponds to a distributed shared memory area, the bus interface creates a remote access command. The send controller constructs a message based on the command created by the bus interface. This message is sent either to an interconnection network, or to a receive controller. The receive controller receives the message and interprets it. An address output by the processor is detected by a cache area access unit, and the cache area in the memory is accessed. When the processor receives an interrupt request while waiting for a response message to a remote read request, an deadlock control unit detects an abnormal end of the remote read request that the remote read has ended in an error, and, controls the processor to process the interrupt request with priority.

Control system for access between processing elements in a parallel

In a computer equipped with a mask register in which is stored mask data indicating, for each array element, whether or not a statement such as an IF statement or an ELSE statement should be applied, the computer having a vector processor executing vector operation processing according to the mask data stored in the mask register, a first executing unit acquires first and second memory areas in which the mask data is saved in a stack formation. A second executing unit generates, when an IF statement appears in execution of a program, mask data indicating truth/falsity of a conditional expression of the IF statement, and saves the mask data indicating the truth/falsity of the conditional expression in the first memory area. A third executing unit reads latest mask data saved in the second memory area in synchronism with a process of the second executing unit. A fourth executing unit performs a bit-base logic operation on the mask data saved by the second executing unit and the mask data read by the third executing unit, stores mask data thus generated and applied to the IF statement in the mask register, and saves the above mask data applied to the above IF statement in the second memory area.

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Kawasaki, Japan

Yoichi Koyanagi