Renesas Electronics Corporation

Nec Electronics Corporation

Nec Corporation

Yoichi Iizuka

Masayasu Komyo

Fukashi Morishita

Satoshi Onishi

Yasuo Ikeda

Takanori Saeki

Yasushi Aoki

Makoto Tanaka

Tadashi Iwasaki

Toshihiro Narisawa

Nobuhiro Ooki

Mikiko Sode

A solid-state image sensor includes a buffer circuit, and an AD conversion circuit. The buffer circuit is connected to a first pixel and a second pixel of a plurality of pixels. The AD conversion circuit converts a voltage signal from the buffer circuit into a digital signal. The buffer circuit includes a voltage holding circuit connected to the first pixel, a voltage holding circuit connected to the second pixel, and a switch circuit. The switch circuit selectively switches the voltage holding circuit which outputs a voltage signal to the AD conversion circuit between the voltage holding circuits. The buffer circuit carries out an operation of holding a voltage signal of the first pixel in the voltage holding circuit and an operation of holding a voltage signal of the second pixel in the voltage holding circuit in parallel with each other.

Solid-state image sensor, imaging device, and AD converter

An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

Integrating analog-to-digital converter and semiconductor device

The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counterfor transmitting a lower bit counter signal JC&#x3c;&#x3e;, a lower bit latch circuitfor outputting a lower bit latch result signal by a lower bit counter signal JC&#x3c;and a lower bit latch signal, a determination circuitfor outputting an upper bit latch signalby a lower bit latch signal, a binary gray converter circuitfor transmitting an upper bit counter signal GR&#x3c;n:&#x3e;, and an upper bit latch circuitfor outputting an upper bit latch result signal by an upper bit counter signal GR&#x3c;n:&#x3e; and an upper bit latch signal

Image sensor with A/D conversion circuit having reduced DNL deterioration

A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about &#xbd;of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.

Semiconductor integrated circuit system with termination circuit

A semiconductor integrated circuit is described. A. transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about &#xbd; of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.

Memory with termination circuit

A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and transmits a first control signal by a second external terminal. When another data is transmitted after the data is transmitted and when a data transmission interval from a time when the data is transmitted to a time when the another data is transmitted is equal to or smaller than a first threshold, the transmitter-receiver continuously outputs, from the first external terminal, a potential level of about &#xbd; of a potential level obtained by adding a first potential level and a second potential level, during the data transmission interval, and changes the second potential level of the first control signal to the first potential level when the data transmission interval exceeds the first threshold.

A data transmitting method used in a semiconductor device having a controller and a transmitter is described. A first write command is output by the controller and then a second write command is output by the controller. An interval time between the first write command and the second write command is calculated. The transmitter is activated by the controller and a first data is transmitted by the transmitter in accordance with the first write command, and then the transmitter is inactivated based on the interval time. Then the transmitter is activated when the transmitter is inactivated. Then, the second data is transmitted by the transmitter in accordance with the second write command.

Semiconductor integrated circuit with data transmitting and receiving circuits

An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element L, and a capacitive element C, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal.

Oscillator and semiconductor integrated circuit device

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Growing community of inventors

Kanagawa, Japan

Yoichi Iizuka