Kabushiki Kaisha Toshiba

Yoichi Hiruta

Naohiko Hirano

Chiaki Takubo

Kazuhide Doi

Takashi Okada

Masayuki Miura

Eiichi Hosomi

Yasuhiro Yamaji

Hiroshi Tazawa

Koji Shibasaki

Tsutomu Nakazawa

Mamoru Sasaki

Katsuto Katoh

Akihiro Mase

Yoshihiro Atsumi

A reel tape includes a base tape for reel winding, a chip mounting section on the base tape, on which a bare chip is to be mounted and an adhesive layer coated on the chip mounting section. The bare chip is provisionally bonded to the chip mounting section with the adhesive layer interposed therebetween such that the bare chip is detachable. Therefore, the bare chip can be detached from the tape for chip testing, for example, and mounted on the tape again after the testing. The reel tape further includes a protector, e.g. a bar, provided on the base tape and along the chip mounting section in a tape conveying direction. The protector prevents the bare chip from contacting an overlaying portion of the base tape when the base tape is wound on a reel.

Reel tape for provisionally supporting a bare chip

A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

Flip-chip connection type semiconductor integrated circuit device

A board body constituting a characteristic evaluation board has a holding section for holding a semiconductor chip therein. The semiconductor chip has a plurality of bumps. The respective bumps of the semiconductor chip are set in contact with corresponding electrodes with the semiconductor chip held in the holding section in the board body. Clamping mechanisms are located on the surface of the board body in the neighborhood of the holding section. The clamping mechanisms press the semiconductor chip held in the holding section. The respective bumps on the semiconductor chip are pressure contacted with the corresponding electrodes. Since the respective bumps are pressure contacted with the corresponding electrodes without using a solder, the respective bumps can be formed of an eutectic solder. The semiconductor chip held in the holding section can readily be taken out of the holding section by opening the clamping mechanisms.

Board for evaluating the characteristics of a semiconductor chip and a

An LSI chip has first electrodes. A chip carrier has a board, second electrodes arranged on a first surface of the board, third electrodes arranged on a second surface of the board, and wires connecting second electrodes to third electrode each other. Bumps combine the first electrodes of the LSI chip with the second electrodes of the chip carrier each other. Resin fills a space between a main surface of the LSI chip and a first surface of the board, so as to fix the bumps to each other. Ball electrodes are combined with third electrodes of the chip carrier.

Semiconductor device having ball grid array

A chip is bonded to a tape for ready handling. A flipping mechanism picks up the chip from the tape and sets it in an inverted state. An aligning/mounting mechanism is adapted to align and accurately mount the chip on associated electrodes of a test board. Another flipping mechanism re-sets a post-tested chip onto the tape conveyed by a conveying mechanism.

Bare chip prober device

In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.

Flip chip mounting type semiconductor device

An Al layer which serves as a lead-out electrode is formed on a semiconductor chip. An insulating layer is formed on the semiconductor chip and the Al layer. The insulating layer has an opening formed in that portion thereof which is located on the Al layer, thereby exposing a portion of the Al layer. A multi-level metal layer (barrier metal layer) is formed on the exposed portion of the Al layer and on that portion of the insulating layer which is located along the edge of the opening. A metallic nitride region is provided between a first-level metal layer in the multi-level metal layer and the insulating layer so as to be selectively formed at or under a peripheral portion of the first-level metal layer. A bump electrode is provided on the multi-level metal layer. The resultant semiconductor device is mounted on a circuit board by flip chip bonding, with the bump electrode interposed therebetween.

Connecting electrode portion in semiconductor device

A semiconductor device includes a semiconductor chip which is connected to a circuit substrate via solder bumps by flip-chip connection, a first encapsulant having a large Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the central portion of the semiconductor chip, and a second encapsulant having a small Young's modulus and filling a space between the semiconductor chip and the circuit substrate in the peripheral portion of the semiconductor chip. A method for manufacturing the semiconductor device includes flowing the second encapsulant into position, but not the first encapsulant.

Flip-chip semiconductor devices having two encapsulants

In bonding the connecting electrodes of adjacent semiconductor chips to each other, a solder layer shaped like a bump is formed on that portion of the connecting electrode which is positioned on the upper surface of the semiconductor chip. The semiconductor chips are positioned close to each other such that the connecting electrodes of these chips are aligned with each other. Then, the solder layer is melted to cause the molten solder to flow along the entire region of the connecting electrode and, thus, to achieve mutual bonding of the connecting electrodes in the entire regions including the upper surface region and the side surface region. The method permits stably bonding semiconductor chips to each other with a high bonding strength, leading to an improved reliability of electric connection in the bonded portion.

Method of manufacturing a semiconductor device

A power source noise suppressing type semiconductor device has: a semiconductor chip formed therein with a first circuit and a second circuit, the semiconductor chip having a plurality of pads on the surface thereof, the pads including at least a first circuit pad electrically connected to the first circuit and a second circuit pad electrically connected to the second circuit; a plurality of leads including at least one power source lead, each of the plurality of leads having an inner lead and an outer lead; and a plurality of bonding wires for electrically connecting the pad to the inner lead of the lead, the first circuit pad being connected to a first connection point of the inner lead of the power source lead by a bonding wire, the second circuit pad being connected to a second connection point of the inner lead of the power source lead by a bonding wire, and the first and second connection points being spaced apart by a distance which allows the mutual inductance between the first and second connection points of the inner lead of the power source lead to become smaller than a self-inductance of the outer lead of the power source lead.

Power source noise suppressing type semiconductor device

A semiconductor integrated circuit device of this invention includes a semiconductor substrate having an active region arranged in a main surface area and an inactive region arranged in a peripheral portion of the main surface area. A semiconductor integrated circuit is formed in the active region in the main surface area of the semiconductor substrate. A connection electrode is formed on the inactive region. One end of a lead is connected to the connection electrode and the other end thereof is arranged to extend to the exterior of the semiconductor substrate. The semiconductor integrated circuit and the connection electrode are electrically connected to each other via an impurity diffusion region. At least the active region of the semiconductor substrate, the connection electrode, part of the lead arranged on the main surface of the semiconductor substrate, and the impurity diffusion region are covered with a sealing body having a sealing substrate.

Semiconductor integrated circuit device having sealing means

Since an electronic device comprises an electronic component, an external connection terminal electrically connected to the electronic component, and an envelope for sealing the electronic part and having a thickness less than about 0.5 mm, the electronic device is miniaturized even in the case where it is provided with a large number of terminals. Further, since the electronic component is sealed by the envelope, moisture, etc. is not admitted into the electronic component, resulting in high reliability. In addition, since the thickness of the envelope is thin, the external terminal can be shortened. Thus, the inductance or capacitance of this terminal can be reduced.

Electronic device having a chip with an external bump terminal equal or

A semiconductor device comprises a printed circuit board with circuit pattern formed thereon, and a semiconductor wafer having terminals installed on its peripheral portion. Semiconductor chips are mounted on one surface or both surfaces of the semiconductor wafer. A connector is installed on the printed circuit board for electrical connection with the terminals. When the terminals are connected to the circuit pattern, the semiconductor wafer is installed substantially vertically on the printed circuit board. Or a semiconductor wafer member is constituted by two semiconductor wafers, and a closed space is internally formed between the two wafers and heat pipes for heat radiation are inserted in the closed space.

Semiconductor device and method for mounting semiconductor wafer

A semiconductor chip is packaged within film carriers which serve as the enclosure of the semiconductor chip. The finished semiconductor device is flexible, bendable, and very thin. In manufacturing this semiconductor device, the process of laminating film carriers, the process of electrically connecting the semiconductor chip and film carriers, and the process of sealing the semiconductor chip, can be performed at the same time, shortening the manufacturing time and reducing manufacturing cost.

Semiconductor device of multichip module-type

There is disclosed a semiconductor device in which the resistance pattern on the semiconductor substrate is formed by the resistance film and the wiring pattern connected to the resistance pattern is formed by the resistance film and the conductive film deposited and formed thereon. Furthermore, a method of manufacturing such a semiconductor device by a photolithographic process is disclosed. In accordance with this method, after the resistance film is formed, a conductive film is formed thereon and the conductive film corresponding to the portion serving as a resistance element is removed. A convex portion may be provided on the insulating substrate, thus to form wiring only on this region or to form wiring only around this region.

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Kashiwa, Japan

Yoichi Hiruta