Nippon Telegraph and Telephone Corporation

Ntt Electronics Corporation

Nippon Telephone and Telegraph Corporation

Yohtaro Umeda

Atsushi Kanda

Makoto Nakamura

Masatoshi Tobayashi

Yoshikazu Urabe

Jun Endou

Hatsushi Iizuka

Yuji Akatsu

Eiji Hyodo

Yuuki Imai

A gain switching determination circuit () compares/determines a comparative input voltage (Vc) from an inter-stage buffer () with a first hysteresis characteristic, and outputs a gain switching signal (SEL) based on the comparison/determination result to first and second transimpedance amplifier core circuits (), thereby switching the gains of the core circuits. This obviates holding a comparison input voltage with long response time in a level holding circuit for gain switching determination, which allows instantaneous gain switching determination and instantaneous response corresponding to burst data.

Transimpedance amplifier

A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.

Driver circuit

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Kanagawa, Japan

Yohtaro Umeda