Intel Corporation

Yohko Mashimoto

Kinya Ichikawa

Kenzo Ishida

Shuji Inoue

Jiro Kubota

Mashahiro Kuroda

Takaya Miwa

Seiichiroh Seki

An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.

Method for producing a multilayer interconnection structure

A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

Printed circuit substrate with solder formed on pad-on-via and

Multiregion solder interconnection structure

A substrate for an integrated circuit package is provided. The substrate includes a first dielectric layer with a first coefficient of thermal expansion. The first dielectric layer has a bottom surface and an inner side surface. The inner side surface defines a first aperture. The substrate also includes a conductive pad having a bottom surface and a side surface. The side surface of the conductive pad engages the inner side surface of the first dielectric layer. The substrate further includes a second dielectric layer having a second coefficient of thermal expansion closely matching the first coefficient of thermal expansion. The second dielectric layer is deposited upon the bottom surface of the first dielectric layer and upon a first portion of the bottom surface of the conductive pad. The first portion of the bottom surface of the conductive pad is adjacent to the side surface of the conductive pad.

Design for flip chip joint pad/LGA pad

An method for depositing solder onto the pad-on and pad-off via contacts of a substrate is disclosed. In one embodiment the present invention includes positioning a mask having a first opening of a first diameter and a second opening of a second diameter over a substrate having both pad-on and pad-off via contacts. The substrate is positioned over the substrate such that the first opening is positioned over the pad-on via contact and the second opening is positioned over the pad-off via contact. Solder of a first volume and solder of a second volume are deposited onto the pad-on and pad-off via contacts, respectively, by forcing a solder paste through the mask openings. In this manner, solder bumps having a uniform height and volume above the pad-on via contact plane is established after reflowing the deposited solder.

Growing community of inventors

Ibaraki, Japan

Yohko Mashimoto