Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Holdings Corporation

Yohei Morishita

Noriaki Saito

Takenori Sakamoto

Yoshito Shimizu

Kiyomichi Araki

Naganori Shirakata

Katsuaki Abe

Junji Sato

Hidekuni Yomo

Hiroyuki Handa

Yoshifumi Hosokawa

Kenta Iwasa

Yuta Moriura

Toru Okino

Ryo Kitamura

Yoshitaka Nakamura

Toru Sakuragawa

Satoshi Morishita

Yasufumi Kawai

Masaki Kanemaru

Hiroyuki Hagino

Kazuma Nishiyasu

Mei Okamoto

Hiroka Shiozaki

Provided is an improved estimation and identification device that estimates the position of a plurality of identification targets and identifies the plurality of identification targets. The estimation and identification device has a configuration comprising: a plurality of tracking devices that emit electromagnetic waves or sound waves and detect the position of an identification target on the basis of reflected electromagnetic waves or sound waves from the identification target holding a wireless transmission terminal; a plurality of wireless communications devices that wirelessly communicate with wireless communications terminals and receive identification information for the wireless communications terminals from the wireless communications terminals; and an analysis circuit that identifies the identification target and estimates the position of the identification target, on the basis of the results of the wireless communications results, the detected position of the identification target, and the identification information.

Estimation and identification device and estimation and identification system

A travel sickness estimation system includes an estimation unit and an output unit. The estimation unit is configured to perform estimation processing of estimating, based on person information indicating conditions of a person who is on board a moving vehicle, whether or not the person is in circumstances that would cause travel sickness for him or her. The output unit is configured to output a result of the estimation processing performed by the estimation unit.

Travel sickness estimation system, moving vehicle, travel sickness estimation method, and travel sickness estimation program

A phase shifter includes a first capacitor connected to a first line to which a first input signal is input, a second capacitor connected to a second line to which a second input signal having a first phase difference with respect to the first input signal is input, and a combining circuit that is connected to the first line and the second line and that outputs a combined signal having a phase determined depending on a first capacitance ratio between the first capacitor and the second capacitor.

Phase shifter and wireless communication apparatus

A gain controller sets a gain code indicating an optimum gain, a cutoff frequency code indicating a cutoff frequency, and a number of bits code indicating a number of bits. An AEQ/VGA gain controller sets a frequency characteristic code indicating a frequency characteristic, a gain code indicating a gain after correction, and a number of bits code indicating a number of bits. An AEQ/VGA amplifies a baseband received signal on the basis of a gain code and corrects a frequency characteristic of the baseband received signal on the basis of a frequency characteristic code. An HPF cuts off a band below a cutoff frequency of an output signal from the AEQ/VGA on the basis of a cutoff frequency code. An ADC quantizes an output signal from the HPF using a number of bits based on a number of bits code and generates a digital received signal.

Radio receiving device and transmitting and receiving device

A switch control circuit includes: a clock generating circuit that generates one or more periodic signals having a predetermined cycle; a clock adjusting circuit that generates one or more control signals by adjusting a bias voltage of the one or more periodic signals and changing an ON period of the one or more periodic signals; and at least one switching circuit including one or more switches that are switched to ON if respective amplitudes of the generated one or more control signals is equal to or higher than a threshold value and that are switched to OFF if the respective amplitudes of the generated one or more control signals is less than the threshold value.

Switch control circuit

A radio receiving apparatus includes an RF front-end unit that performs gain control and downconversion on a received signal, an analog equalizer that performs an analog equalization process on an output signal from the RF front-end unit in accordance with a coefficient of analog equalization, an analog/digital converter that samples and quantizes an output signal from the analog equalizer, a digital equalizer that performs a digital equalization process on an output signal from the analog/digital converter in accordance with a coefficient of digital equalization, and a coefficient-of-equalization calculator that calculates the coefficient of analog equalization and the coefficient of digital equalization by estimating frequency characteristics with use of the output signal from the analog/digital converter.

Radio receiving apparatus

An equalizer circuit includes an phase-to-phase connectors including an phase-to-phase capacitor and four phase-to-phase switches, four output buffers, and control signal generation circuitry. One terminal of each phase-to-phase switches is connected to one of four connection paths on which four conversion signals being different in phase by 90&#xb0; are input. The other one terminal of each phase-to-phase switches is connected to the phase-to-phase capacitor. Each output buffer is connected to one of the four connection paths and outputs an output signal. The control signal generation circuitry outputs control signals to control turning-on/off of the respective four phase-to-phase switches. A closing of the first, second, third, and fourth phase-to-phase switches are started from any one of phase-to-phase switches in one of a first ascending circulation and a first descending circulation based on the 4-phase control signals.

Equalizer circuit and receiving apparatus using the same

A discrete-time analog circuit comprises: a voltage-current conversion circuit that converts an input voltage signal into a current signal and outputs the current signal; and a charge inverting circuit that is connected to an output terminal of the voltage-current conversion circuit to perform charge sharing. The charge inverting circuit includesM capacitors (M is an integer greater than or equal to 1) that are provided parallel to each other. In accordance with a predetermined sampling interval, one of theM capacitors repeats: (1) sharing input charge that is input by the current signal, (2) holding at least part of the input charge, (3) inverting a polarity of the held charge and connecting to the output terminal to share the held charge, and (4) holding remaining charge. At time period when one of theM capacitors is connected to the output terminal, the other capacitor(s) of theM capacitors is not connected to either of an input terminal and the output terminal.

Discrete-time analog circuit, transmitting device, and receiving device

There is provided a variable gain multistage amplifier including: an input terminal to which the input signal is input; multistage amplifiers amplify the input signal, the multistage amplifiers being connected in series; and an output terminal that outputs the amplified signal, and

Variable gain multistage amplifier and receiver

The sampling mixer circuit comprises: a clock generating circuit that outputs four-phase control signals the periods of which are in accordance with the carrier frequency of an input signal and the phases of which are different from one another; a voltage-to-current converting circuit that converts a voltage signal based on the input signal to a current signal; four-system charge sharing circuits in which the current signal as converted is input to a plurality of capacitors in accordance with the different phases based on the four-phase control signals and in which charges are exchanged among the plurality of capacitors; and a phase-to-phase capacitor that is selectively connected, on the basis of the four-phase control signals, to the respective ones of nodes, which are other than the input nodes of the current signal, in the four-system charge sharing circuits.

Sampling mixer circuit and receiver

A sampling circuit is provided that includes a first sampling circuit that shifts a frequency, at which a gain of a frequency characteristic is maximized, to a lower frequency side, and a second sampling circuit that shifts the frequency, at which the gain of the frequency characteristic is maximized, to a higher frequency side. The sampling circuit also includes an output section provided in an output side of the first sampling circuit and an output side of the second sampling circuit, and outputs a sum or a difference between an output from the first sampling circuit and an output from the second sampling circuit.

Direct sampling circuit and receiver

The discrete time analog circuit () is provided with: a rotate capacitor circuit (); an amplifier () that is connected to the input line or the output line of the rotate capacitor (), and amplifies the input potential or input charge; a coefficient circuit () that is positioned in series with the amplifier (), and has two history capacitors (--) positioned parallel to each other; a first active capacitor among the two history capacitors (--) that is connected to and charges the amplifier (); and a clock generation circuit () that is connected to the input line or the output line without the involvement of the amplifier (), and that sequentially changes the pairing of the rotate capacitor circuit () a second active capacitor, which shares a charge with the rotate capacitor circuit ().

Discrete time analog circuit and receiver using same

A sampling circuit and a receiver are provided having a high flexibility of filter design and excellent characteristics for removing an interfering wave. Provided also are a sampling circuit and a receiver having a low level of the higher harmonic spurious. The sampling circuit includes a charge sampling circuit, which executes sampling of an input signal, and a plurality of charge sharing circuits connected in parallel to the output stage of the charge sampling circuit. The charge sharing circuits include a charge sharing circuit group having transmission functions different from one another, a synthesis circuit, which is arranged at the output side of the charge sharing circuit group and synthesizes the outputs of the charge sharing circuits, and a digital control unit, which outputs a control signal for controlling the operation of the charge sharing circuit group and the synthesis circuit.

Sampling circuit and receiver using same

A sampling circuit and a receiver have a high level of filter design flexibility and excellent image rejection characteristics. Signals with phases that differ by 90&#xb0; are sampled using an IQ generating circuit and are weighted by each of multiple parallel-connected discrete-time circuits, and the result of addition by an output adding circuit is ultimately output. Alternatively, a configuration in which the multiple parallel-connected discrete-time circuits and the output adding circuit are cascade-connected is adopted, so that frequency characteristics having an attenuation pole to one side can be achieved and excellent image rejection characteristics can be obtained.

Sampling circuit and receiver utilizing the same

A sampling circuit and a receiver, with relatively simple configurations, and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits, a charging switch is controlled on and off using one of four-phase control signals. A rotate capacitor shares electrical charge accumulated in an IQ generating circuit via the charging switch. A dump switch is controlled on and off using a different signal from the control signal used to control the charging switch on and off, among the four-phase control signals. A buffer capacitor shares electrical charge with the rotate capacitor via the dump switch to form an output value.

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Kanagawa, Japan

Yohei Morishita