Thine Electronics, Inc.

Yohei Ishizone

Satoshi Miura

Seiichi Ozawa

Shuhei Yamamoto

Tetsuya Iizuka

Jun-ichi Okamura

Shunichi Kubo

Kunihiro Asada

Hironobu Akita

Yoshimichi Murakami

Akita Hironobu

A clock data recovery devicegenerates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector, a phase delay unit, a time measurement unit, a phase selector, an edge detector, a polarity detector, a logic inverter, and a data output unit. The signal selector, the phase delay unit, the time measurement unit, and the phase selectorconstitute a clock-generation deviceA. The phase delay unitincludes a plurality of cascaded delay elementsto. The phase selectorselects a signal output from the delay element in a position corresponding to a unit interval time among the delay elementsto, and outputs the signal as a feedback clock Feedback Clock.

Clock-generating device and clock data recovery device

Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication systemsends, to the receiving device, a serial data signal Sthat is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sin the transmission deviceis changed. The receiving devicethat received the serial data signal Sreceives training data Tfrom the transmission devicewhen it is determined that the serial data signal Sis a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Transmission device, receiving device and communication system

[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Transmitter circuit, receiver circuit, clock data recovery phase locked loop circuit, data transfer method and data transfer system

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Chiyoda-ku, Japan

Yohei Ishizone