Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Yohei Akita

Kazuo Yano

Mitsuru Hiraki

Naoki Katoh

Naoki Kato

Hirotaka Hara

Tadashi Kameyama

Takanobu Naruse

Hiroshi Tanaka

Fumio Arakawa

Takanobu Tsunoda

Tetsuro Honmura

A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.

Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply voltage of semiconductor device

A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFFbetween the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

Semiconductor integrated circuit including multiple basic cells formed in arrays

This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.

Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit

A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a communication line to complete the system design verification. A system verification equipment to be operated by the IP provider receives from the system designer across the communication line an input vector at time n to a module provided to the system designer who designed the system integrated using one or more provided IP modules. After simulating the module operation with the input vector, the verification equipment returns an output vector obtained at time n+1 to the system designer over the communication line. The verification equipment examines the input vectors to the provided IP modules and records statistics information thereof, based on which the provider will quantitatively understand how the provided modules have been used. Such information is used by the provider to determine the specifications of modules to be provided next time and to market modules meeting user needs. The verification equipment determines the service charge for each IP user by the quantity of load worked on its verification system to fulfill the service, according to the quantity of input vector data transmitted to the equipment by the user. Furthermore, the verification equipment encrypts vector data before transmitting it across the communication line and decrypts vector data after receiving it over the line such that the data is prevented from intercepted by a third party.

System verification equipment, system verification method and LSI manufacturing method using the system verification equipment

There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function. A logic circuit having the circuitry shown in FIG.will be described briefly. Two transmission gates TG(TG) and TGand two inverters IVand IVare used to define a data propagation path from an input port I(I) to an output port O. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG(TG) is controlled using a NOR circuitthat inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuitthat inputs the clock CLK and the select signal sel). The transmission gate TGis controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output. When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.

Logic circuit

Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.

Growing community of inventors

Kokubunji, Japan

Yohei Akita