Rambus Inc.

Xilinx, Inc.

Yohan Usthavia Frans

Nhat M Nguyen

Simon Li

Kun-Yung Chang

Brian S Leibowitz

Hae-Chang Lee

Akash Bansal

Wayne Frederick Ellis

Kee Hian Tan

Mayank Raj

Yu Xu

Hongtao Zhang

Winson Lin

Todd W Bystrom

Alan C Wong

Christopher J Borrelli

Parag Upadhyaya

Jun Y Kim

Geoffrey Zhang

Yueyong Wang

Dennis Kim

Chuan Xie

Caleb S Leung

Ping-Chuan Chiang

Huy M Nguyen

Stanley Yuanshih Chen

Yipeng Wang

Arianne Roldan

Jared L Zerbe

John Eric Linstadt

Kevin S Donnelly

Suresh Ramalingam

Jaeha Kim

Kishore Ven Kasamsetty

Barry William Daly

Jason C Wei

Didem Z Turker Melek

Arun Vaidyanath

Siok Wei Lim

Nakul Narang

Kok Lim Chan

Chin Yang Koay

Hongyuan Zhao

Michael Green

Geoff Zhang

Hai Bing Zhao

Kyung Suk Oh

Cheng-Hsiang Hsieh

Wayne S Richardson

Gamal Refai-Ahmed

Lawrence Lai

Edward Kihyen Lee

Kambiz Kaviani

Amitava Majumdar

Zhaoyin D Wu

Pravin Kumar Venkatesan

Michael O Jenkins

Adebabay M Bekele

Shuxian Wu

Richard William Swanson

Xin X Wu

Jing Jing

Jinyung Namkoong

Eric Linstadt

Hiva Hedayati

Gourav Modi

Siva Charan Nimmagadda

Hong Sik Ahn

Zhaowen Wang

Ivan O Madrigal

Baanurathan Sadasivam

Murtuza Z Cutleriwala

Ken Chang

Ping Chuan Chiang

Sukruth Pattanagiri Giriyappa

Sandeep Kumar

Sukruth Pattanagiri

Muqseed Mohammad

Haibing Zhao

Eric Lindstadt

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Interface with variable data rate

A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die

The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

Timing-drift calibration

An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.

Circuits and methods for wavelength locking of optical receiver WDM filters

An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

Frequency detector for clock data recovery

A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Synchronous wired-or ACK status for memory with variable write latency

Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

Heterogeneous integration module comprising thermal management apparatus

An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.

Integrated electrical/optical interface with two-tiered packaging

Synchronous wired-OR ACK status for memory with variable write latency

Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

Inductor design in active 3D stacking technology

Growing community of inventors

Sunnyvale, CA, United States of America

Yohan Usthavia Frans