Apple Inc.

Yohan Rajan

Paolo Di Febbo

Chaminda Nalaka Vidanagamachchi

Waleed Abdulla

Jerome C Tu

Anselm Grundhoefer

Jae Hwang Lee

Justin J Schwab

Yoshikazu Shinohara

Anthony Ghannoum

Nathanael D Parkhill

Andrew K McMahon

Nalaka Vidanagamachchi

Cam Harder

Moinul H Khan

Arthur Yasheng Zhang

Siddharth Shankar Hazra

Mohammad Ghasemzadeh

Yanli Zhang

William J Dobbie

Dk Kalinowski

D K Kalinowski

Recording indicators for devices with cameras that provide protection from tampering so that the recording indicators cannot be easily disabled or masked. Recording indicators that are external to the camera lens and that emit visible light in an encrypted pattern are described. The device may process captured frames to detect the encrypted pattern; if the encrypted pattern cannot be detected, recording is disabled. In addition, modular accessories are described that the user has to attach to the device to enable recording; the presence of the modular attachment indicates to persons in the environment that they may be being recorded.

External recording indicators

An apparatus includes a primary camera sensor configured to capture images having a first resolution, a primary processing circuit configured to process images captured by the primary camera sensor, a secondary camera sensor configured to capture images having a second resolution, and a secondary processing circuit configured to process images captured by the secondary camera sensor. In response to a determination that a particular object of interest is included in a particular image, the secondary processing circuit may be further configured to cause the primary processing circuit and the primary camera sensor to exit a reduced power mode. The primary camera sensor may be further configured, in response to the exiting, to capture a different image. The primary processing circuit may also be configured to process the different image to validate the particular object of interest.

Video monitoring using a hierarchical combination of camera sensors

Embodiments relate to a neural processor circuit that may include a fetch circuit that fetches coefficient data of a machine learning model from a memory source. The neural processor circuit may also include one or more neural engine circuits that are coupled to the fetch circuit. A neural engine circuit may include a buffer circuit that stores the coefficient data. The neural engine circuit may also include a coefficient organizing circuit that generates at least a first mapping and a second mapping of the stored coefficient data according to one or more control signals. The neural engine may also include a computation circuit that receives and processes at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.

Mappable filter for neural processor circuit

In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

Hybrid memory in a dynamically power gated hardware accelerator

Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

Dynamic variable bit width neural processor

According to various implementations, a method is performed at an electronic device including one or more processors, non-transitory memory, and one or more displays. The method includes, while presenting a virtual environment, via the one or more displays, obtaining a request for interaction from an external source. The virtual environment includes a first plurality of available presentation regions and a second plurality of unavailable presentation regions. The method includes determining whether the request for interaction from the external source satisfies one or more interaction criteria. The method includes presenting, via the one or more displays, an avatar associated with the external source at one of the first plurality of available presentation regions within the virtual environment, in response to determining that the external source satisfies the one or more interaction criteria.

Method and device for surfacing physical environment interactions during simulated reality sessions

Various implementations disclosed herein include multi-scale visual markers that convey information in multiple sets of markings using different respective appearance attributes. In some implementations, the appearance attribute of the markings of a first set of markings corresponds to a first encoding parameter and the appearance attribute of markings of a second set of markings corresponds to a second encoding parameter different from the first encoding parameter. In some implementations, the first set of markings encode first data and the second set of markings are different than the first set of markings and encode second data. In some implementations, the different appearance attributes are different scales (e.g., different sizes, different numbers of markings per unit of space, different contrast, different color characteristics, different wavelengths, different image sensor types, etc.).

Visual marker

Recording indicators for devices with cameras that provide protection from tampering so that the recording indicators cannot be easily disabled or masked. Recording indicators that are integrated in a device's camera and that emit visible light through the camera lens aperture are described. In addition, modular accessories are described that the user has to attach to the device to enable recording; the presence of the modular attachment indicates to persons in the environment that they may be being recorded.

Recording indicators

In an embodiment, a local memory that is dedicated to one or more hardware accelerators is divided into a plurality of independently powerable sections. That is, one or more of the sections may be powered on while other ones of the plurality of sections are powered off. The hardware accelerators receive instruction words from one or more central processing units (CPUs). The instruction words may include a field that specifies an amount of the memory that is used when processing the first instruction word, and the power control circuit may be configured to power a subset of the plurality of sections to provide sufficient memory for the instruction word based on the field, while one or more of the plurality of sections are powered off.

Dynamic granular memory power gating for hardware accelerators

Various implementations disclosed herein include devices, systems, and methods that dynamically-size zones used in foveated rendering of content that includes text. In some implementations, this involves adjusting the size of a first zone, e.g., a foveated gaze zone (FGZ), based on the apparent size of text from a viewpoint. For example, a FGZ may be increased or decreased in width, height, diameter, or other size attribute based on determining an angle subtended by one or more individual glyphs of the text from the viewpoint. Various implementations disclosed herein include devices, systems, and methods that select a text-rendering algorithm based on a relationship between (a) the rendering resolution of a portion of an image corresponding to a part of a glyph and (b) the size that the part of the glyph will occupy in the image.

Rendering computer-generated reality text

In one implementation, a method includes: displaying simulated reality (SR) content; determining whether an object in a physical environment satisfies one or more interaction criteria; and changing display of the SR content from a first view to a second view, in response to determining that the object in the physical environment satisfies the one or more interaction criteria, wherein, in the first view, the object in the physical environment is occluded by the SR content, and wherein the second view reduces occlusion of the object in the physical environment by the SR content.

Growing community of inventors

Cupertino, CA, United States of America

Yohan Rajan