Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Korea Advanced Institute of Science and Technology

Yohan Lee

Sangwan Nam

Jaeyoung Kim

Jaesung Lee

Jaeho Lee

Soyoung Lee

Sang-Wan Nam

Donghyun Yeom

Jongkon Bae

Dongkyoon Han

Yunpyo Hong

Jaeduk Yu

Yonghyuk Choi

Donghwy Kim

Hanyuool Kim

Sangwon Park

Jinhyun Kim

Chaehoon Kim

Sangheon Kim

Jaebong Chun

Jungchul An

Mooyoung Kim

Jin-Yub Lee

Kwangtai Kim

Sangsoo Park

Geon-Soo Kim

Dasom Lee

Taekyoung Kim

Sangwoo Lee

Jungeun Lee

Sang-Won Park

Junho Park

Jong-Kon Bae

Moonsoo Kim

Jongwu Baek

Ho-Jun Lee

Jiyong Kim

Hyunyeul Lee

Won-Tae Kim

Hyunkyoung Kim

Byungduk Yang

Jonghoon Park

Hyesoon Jeong

Taehyeong Kim

Junghun Kim

Jiho Cho

Jiwon Choi

In-Hyung Jung

Hanchoon Lee

Joo Yeon Park

Jaehyeon Kang

Boyeon Na

Seungkyu Choi

BongJun Kim

SeHyeon Kim

Donghui Kim

Hyungjin Sung

Sunggoon Park

Hongseong Kim

Suhyeong Lee

Duhyun Kim

Youngeun Han

Dongsub Kim

MinWoo Jeong

Hojin Kim

Jaebok Lee

Sunok Kim

Venkataramana Gangasani

Jungbae Bae

Giyong Lee

Hyunjun Park

Hongkook Lee

Sungwhan Seo

Sejun Song

Youngjay Lee

Changjin Kim

Jong-Wu Baek

Younghee Ha

Jisun Park

Dongha Shin

Seungyong Lee

Eunhyang Park

Sangseol Lee

Eunyeoung Choi

Wonsik Song

Youngsu Lee

Sang-wan Nam

Sunkyoung Kim

Siyoung Choi

Minseung Kim

Dojeon Lee

Eunsook Seo

Seungyeon Chung

Yongseok Cho

Namyun Kim

Sanggi Hong

Sang-won Park

Jihoon Jeon

Jungkyun Ryu

Yeonsun Choi

A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.

Memory device including string select transistors having different threshold voltages and method of operating the memory device

Provided is an operating method of a nonvolatile memory device. The operating method includes receiving a read command, increasing a voltage applied to a plurality of unselected ground selection lines from an off voltage to an on voltage during a word line setup period, applying a first voltage to a first selected ground selection line corresponding to a first process characteristic, until a first time in the word line setup period, applying a second voltage to the first selected ground selection line after the first time in the word line setup period, applying the first voltage to a second selected ground selection line corresponding to a second process characteristic, until a second time earlier than the first time in the word line setup period, and applying the second voltage to the second selected ground selection line after the second time in the word line setup period.

Nonvolatile memory device and operating method thereof

A robot includes: a camera; a driver configured to control a motion of the robot; a memory configured to store information on a plurality of motions of the robot and a plurality of emotional states of a pet corresponding to the plurality of motions of the robot; and a processor connected to the driver, the camera, and the memory, wherein the processor is configured to: obtain at least one image of the pet through the camera, identify, based on the obtained at least one image the pet and the information stored in the memory, an emotional state of the pet from among the plurality of emotional states of the pet, identify, based on the information stored in the memory, a motion of the robot corresponding to the identified emotional state, from among the plurality of motions, and control the driver to cause the robot to perform the identified motion of the robot.

Robot for expressing emotional state of pet and control method thereof

An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.

Non-volatile memory device and programming method thereof

Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

Operation method of memory device and operation method of memory system including the same

According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.

Non-volatile memory device including multi-stack memory block and operating method thereof

A heat transfer pipe includes an outer pipe having a space therein and extending a first direction, a core disposed in the space inside the outer pipe, defining a refrigerant flow space through which a refrigerant flows between an inner surface of the outer pipe and the core, and extending in the first direction, and a resistor disposed in the refrigerant flow space and having a spiral shape with a central axis disposed to be parallel to the first direction.

Heat transfer pipe and heat exchanger for chiller

A flash memory device is provided. The flash memory device includes: a first memory cell; a second memory cell on the first memory cell; and a third memory cell between the first memory cell and the second memory cell. The first memory cell, the second memory cell and the third memory cell share a channel. The third memory cell is configured to block channel sharing between the first memory cell and the second memory cell based on a channel separation voltage provided in first to k-th program loops. The third memory cell is configured to connect the channel sharing between the first memory cell and the second memory cell based on a channel connection voltage provided to the third memory cell in a (k+1)-th program loop.

Flash memory device having multi-stack structure and channel separation method thereof

A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

Nonvolatile memory device having multi-stack memory block and method of operating the same

A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.

Nonvolatile memory device with configuration to apply adjustable voltage to pass transistor gate

A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.

Semiconductor device and massive data storage system including the same

Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

Non-volatile memory device

A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

Nonvolatile memory device and method of programming in a nonvolatile memory

A flow disturbance apparatus includes: a refrigerant pipe having a flow space in which refrigerant flows; and at least one disturbance member disposed inside the refrigerant pipe that is vibrated by the flow of refrigerant in the refrigerant pipe to disturb the refrigerant flowing in the refrigerant pipe.

Flow disturbance apparatus and air conditioner comprising the same

An electronic device is provided. The electronic device includes a housing, a display rollable into the housing, and a display driver circuitry operably coupled to the display. The display driver circuitry is configured to display, while the electronic device is in a first state in which a first display area of the display is exposed and a second display area of the display adjacent to the first display area is rolled into the housing, a first image in the exposed first display area, obtain, a second image based on applying a first weight to a pixel value of a first pixel of a first horizontal line and applying a second weight less than the first weight to a pixel value of a second pixel of the first horizontal line, and display, while displaying the first image, the second image in the second display area rolled into the housing.

Electronic device, method, and computer-readable storage medium for reducing afterimage in display area

Growing community of inventors

Seoul, South Korea

Yohan Lee