Arm Limited

Yohan Fernand Fargeix

Albin Pierrick Tonnerre

Luca Nassi

Geoffray Lacourba

Paolo Monti

Abhishek Raja

Lucas Garcia

Ilaria Bosco

Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus comprises allocation circuitry configured to allocate store data comprising N portions in a store buffer. The store buffer comprises a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, wherein a given address entry is indicative of a memory address at which the store data is to be stored and is associated with N indications identifying one or more of the data entries that contain the store data. The allocation circuitry is responsive to a determination that M portions of the N portions of the store data each comprise duplicate data to set M indications of the N indications to identify a given data entry holding the duplicate data.

Allocation of store buffer entries

An apparatus is provided. Delegable memory accesses are offloaded to be performed by an external processing apparatus, whereas non-delegable memory accesses are performed locally. Nonetheless, an ordering requirement may still be enforced between them. The apparatus comprises tracking circuitry to maintain tracking information related to delegable memory accesses separately from tracking information related to non-delegable memory accesses. Order enforcement circuitry may enforce an ordering requirement between a non-delegable memory access and a delegable memory access based on a lookup of the tracking information.

Order enforcement for delegable memory accesses

Apparatuses and methods relating to controlling cache evictions are disclosed. Processing circuitry which execute instructions out-of-order is provided with a private cache into which blocks of data are copied from a shared storage location to which the processing circuitry shares access. The processing circuitry also has a read-after-read buffer, into which an entry is allocated when out-of-order execution of a load instruction occurs comprising an address accessed by the load instruction. The address remains as a valid entry in the read-after-read buffer until the load instruction is committed. Eviction of an eviction candidate block of data from the private cache to the shared storage location is controlled in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer.

Cache eviction control for a private cache in an out-of-order data processing apparatus

Growing community of inventors

Nice, France

Yohan Fernand Fargeix