Micron Technology Incorporated

Sony Semiconductor Solutions Corporation

Yogesh Luthra

Makoto Kitagawa

Serguei Okhonin

Mikhail Nagoga

Xiaojiang Guo

Viktor Koldiaev

Kim-Fung Chan

Michael Allen Van Buskirk

Eric Carman

David Edward Fisch

Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.

Level shifters, memory systems, and level shifting methods

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.

Memory systems and memory programming methods

Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the programming operation and an unselected memory cell not targeted for the programming operation, and the second access line coupled to memory cells not targeted for the programming operation. After increasing the voltage applied to the first access line, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage and increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage.

Methods of operating a memory during a programming operation

Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected access line from a first voltage while maintaining a voltage applied to an unselected access line at the first voltage. The selected access line is connected to a control gate of a target memory cell of a string of series-connected memory cells that is targeted for programming during the programming operation and the unselected access line is connected to a control gate of a second memory cell of the string of series-connected memory cells that is untargeted for programming during the programming operation. After the voltage applied to the selected access line reaches a second voltage, the methods further include increasing the voltage applied to the unselected access line from the first voltage while increasing the voltage applied to the selected access line from the second voltage.

Memory devices and methods of their operation during a programming operation

A memory includes a plurality of replacement word lines interspersed among the plurality of word lines. The memory also includes a word line control circuit configured to apply different voltages to different word lines of the plurality of word lines based on positions of the word lines, and to replace a defective word line of the plurality of word lines with a replacement word line.

Memory having a plurality of memory cells and a plurality of word lines

In an example, a method may include increasing a voltage applied to an unprogrammed first memory cell in a string of series-connected memory cells from a first voltage to a second voltage while a voltage applied to second memory cells in the string of series-connected memory cells is at the first voltage and increasing the voltage applied to the second memory cells from the first voltage to a pass voltage concurrently with increasing the voltage applied to the unprogrammed first memory cell from the second voltage to a program voltage.

Program inhibiting in memory devices

Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data.

Memory devices, memory device operational methods, and memory device implementation methods

Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

Techniques for providing a direct injection semiconductor memory device

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.

Techniques for providing a semiconductor memory device

Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region.

Growing community of inventors

San Jose, CA, United States of America

Yogesh Luthra