Sima Technologies, Inc.

Xilinx, Inc.

Yogesh Laxmikant Chobe

Nishit Harshad Shah

Srivathsa Dhruvanarayan

Kavitha Prasad

Reed Kotler

Moenes Zaher Iskarous

Spenser Don Gilliland

Sedny S J Attia

Sundararajarao Mohan

L James Hwang

Vinod Kumar Kathail

Bradley L Taylor

Hua Sun

Jorge Ernesto Carrillo

Tom Shui

A compiler receives a description of a machine learning network and generates a computer program that implements the machine learning network. The computer program includes statically scheduled instructions that are executed by a mesh of processing elements (Tiles). The instructions executed by the Tiles are statically scheduled because the compiler can determine which instructions are executed by which Tiles at what times. For example, for the statically scheduled instructions, there are no conditions, branching or data dependencies that can be resolved only at run-time, and which would affect the timing and order of the execution of the instructions.

Machine learning network implemented by statically scheduled instructions, with system-on-chip

Machine learning network implemented by statically scheduled instructions, with MLA chip

Machine learning network implemented by statically scheduled instructions, with compiler

Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

Automatic implementation of a customized system-on-chip

Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

Hardware and software cosynthesis performance estimation

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Santa Clara, CA, United States of America

Yogesh Laxmikant Chobe