Analog Devices,inc.

Analog Devices Global Unlimited Company

Analog Devices International Unlimited Company

Yogesh Jayaraman Sharma

Arthur Joseph Kalb

Jochen Schmitt

Nathan R Carter

Paul R Blanchard

Jonathan Ephraim David Hurwitz

Bin Shao

Marvin Liu Shu

Boris Lerner

Harvey Weinberg

Teera Songatikamas

Kenji Tomiyoshi

Sefa Demirtas

James Zhao

Atsushi Matamura

Victor L Iseli

Todd Thomas

Brendan Cronin

Paul Blanchard, Iii

Reed W Adams

Arthur J Kalb

Paul Blanchard

A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors.

Magnetic sensor systems

Magnetic sensors may be positioned around an opening for a wire to measure the current flowing through the wire. A non-symmetric positioning of the sensors around the target measurement zone can enable an expanded measurement zone compared to conventional current measurement devices. Further, some sensors may be paired such that a hypothetical line connecting the sensors is tangential to the target measurement zone. Other sensors may be paired such that a hypothetical line between the sensors crosses the target measurement zone. The different pairs of the sensors can enable a reduction in the impact of stray field interference on the measurement of the current flowing through the wire.

Current measuring apparatus and methods

Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements.

Current measurement using magnetic sensors and contour intervals

A sigma-delta ADC circuit with an analog loop filter circuit can be multiplexed between different inputs by flushing the memory of the analog loop filter integrators and the digital decimation filter and filling it with new data for the current input. However, filling the memory can be slow with respect to the sampling frequency because the information about past history has to be built up before meaningful output data can be generated. Thus, the multiplexing rate between channels using a sigma-delta ADC circuit can be slowed by such memory flushing. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques can provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and that can multiplex over a number of channels dynamically.

Multiplexed sigma-delta analog-to-digital converter

An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.

Quantization noise cancellation in a feedback loop

An analog front end system can include a filter bypass switch connected in a boot-strapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage. Using bootstrapped switches can allow both the charge injection and capacitive coupling of the bypass switches of a differential anti-alias filter (AAF) to be common mode. A differential input signal of the ADC is not affected by the charge injection and capacitive coupling of the bypass switches in the AAF filter to a first order.

Dynamic anti-alias filter for analog-to-digital converter front end

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

High gain load circuit for a differential pair using depletion mode transistors

A low power high precision mixed signal analog to digital converter is provided for processing biometric signals in the presence of a large interferer signal for cableless patient monitoring; a capacitive difference circuit produces an analog difference signal by differencing an analog feedback loop signal and an input signal; an analog-to-digital converter sigma delta converter produces a digital version of the difference signal, a digital feedback loop includes a digital integrator and a capacitive digital-to-analog converter configured to produce the analog loop feedback signal based upon the digital version of the difference.

ADC with capacitive difference circuit and digital sigma-delta feedback

In an embodiment, a body of apparatus includes an opening, such as a V-shaped jaw, that deterministically locates a position of a wire in at least one dimension when the wire is placed in the opening. The apparatus also includes a plurality of sensors. At least one differential signal can be generated from signals from magnetic sensors, such as anisotropic magnetoresistance (AMR) sensors, of the plurality of sensors to cancel out common mode interference. An additional sensor of the plurality of sensors provides an output from which the location of the wire in another dimension is determined. The current flowing through the wire can be derived from at least the at least one differential signal and the location of the wire the other dimension.

Apparatus and methods for measuring current

One aspect of this disclosure is a transimpedance amplifier circuit with multiple resistive feedback loops can be implemented with multiple Kelvin sensing channels. A transimpedance amplifier and multiple Kelvin sensing channels can be implemented on a single die having multiple contacts, such as pins, for connecting multiple resistors to the Kelvin sensing channels. The Kelvin sensing channels can be implemented with T-junction switch networks in certain embodiments.

Wide range transimpedance amplifier

Practical electronics such as amplifiers or voltage references can have circuit imbalances due to manufacturing imperfections. For example, amplifiers can have an undesirable offset voltage. The offset voltage might also drift with temperature making the design of these devices difficult. Disclosed are techniques which decrease the amount of offset voltage which provide predictability of device parameters over a range of temperatures.

Apparatus and method of temperature drift compensation

An ESD protection circuit for a switching power converter which includes a high-side switching element connected between a supply voltage and the switching node, and a low-side switching element connected between the switching node and a common node. A current conduction path couples an ESD event that occurs on the switching node to an ESD sense node, and an ESD sensing circuit coupled to the sense node generates a trigger signal when an ESD event is sensed. A first logic gate keeps the high-side switching element off when the trigger signal indicates the sensing of an ESD event, and a second logic gate causes the low-side switching element to turn on when an ESD event is sensed such that the low-side switching element provides a conductive discharge path between the switching node and common node.

ESD protection circuit for a switching power converter

A current limit scheme for current-mode DC-DC converters. The current limit scheme is used to limit the current through the inductor during a current limit event. Current flows through the inductor alternately from first and second power devices, with one of said devices operating in the on-state while the other is in the off-state. The current through the second power device is sensed and tracked if the peak inductor current exceeds a particular value. The inductor current is regulated by modulating the on-time of the first power device that delivers current from the input voltage source to the output through the inductor. Thus, the modulator adjusts the on-time of the first power device using past and present information related to the current flowing through the second power device and the instantaneous output voltage of the converter to limit the peak inductor current from exceeding a maximum value.

Growing community of inventors

Santa Clara, CA, United States of America

Yogesh Jayaraman Sharma