Intel Corporation

Ampere Computing LLC

Yogesh Bansal

Gilbert M Wolrich

Wajdi K Feghali

Kirk S Yap

Ankush Varma

Nikhil Gupta

Harb Abdulhamid

Ujjwal Gupta

Sachhidh Kannan

Nikethan Shivanand Baligar

Vanshidhar Konda

Vinodh Gopal

Krishnakanth Venkata Sistla

Andrew J Herdrich

Vivek Garg

Dean A Mulla

Swadesh Choudhary

Olivia Wu

Jason Seung-Min Kim

Lakshmipriya Seshan

Nazar Syed Haider

Nitin N Garegrat

Ripan Das

Andrew Yang

Adwait Purandare

Sundar Ramani

Suresh Chemudupati

Aman Sewani

Eric Dehaemer

Stephanie L Hirnak

Makaram Raghunandan

Rupal Parikh

Nilanjan Palit

Pavithra Sampath

Sebastien Hily

Stanley Chen

Tom Schebye

Mrinal Iyer

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Mayank Kaushik

Phani Kumar Kandula

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

Performance level control in a data processing apparatus

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.

Low-impact firmware update

Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.

System-on-chip management controller

Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

Software assisted power management

In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Method for processing multiple operations

A method which includes receiving a request to perform encapsulating security payload (ESP) processing for data exchanged between a node and an other node over a secure network connection established via an Internet Protocol security (IPsec) security association. Information associated with the IPsec security association is obtained based on the request. The information indicates a prepend data unit size for an initialization vector, a generated data unit size for the initialization vector and an append data unit size for the initialization vector. A composition of each initialization vector included with encrypted data exchanged between the node and the other node based, at least in part, on the prepend, generated and append data unit size for the initialization vector is then determined.

Determining composition of an initialization vector for encapsulating security payload processing

The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Storage accelerator

Growing community of inventors

Ashland, MA, United States of America

Yogesh Bansal