Intel Corporation

Yoel Krupnik

Ariel Cohen

Ram Livne

Yitzhak Elhanan Schifmann

Ahmad B Khairi

Roee Eitan

Adee Ofir Ran

Dror Lazar

Lior Horwitz

Gabi Glasser

Ro'ee Eitan

Vladislav Tsirkin

Tomer Fael

Alexander Pogrebinsky

Emmanuel Franck

Gal Alkon

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

Differential source follower with current steering devices

An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

Analog to digital convertor (ADC) using a common input stage and multiple parallel comparators

One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

Slicer and decision feedback equalization circuitry

Architecture and corresponding methods share resources and synchronize counters in high-speed network integrated circuits. The architecture has at least one counter group comprising several registers, each with two ports. One port receives networking events (e.g., receipt of an-error packet, transmission of a good packet, etc.) via a tri-state bus. The registers in each counter group use a shared hardware memory element, which adds the events for each counter group. The second port is available for asynchronous external read accesses via a second tri-state bus. The architecture synchronizes read requests with events such that read accesses occur during gaps in events. The registers are assigned to several mutually exclusive counter groups such that no two registers in the counter group increment in a basic clock cycle.

Statistical counters in high speed network integrated circuits

A differential envelope detector for detecting the envelope of a received differential signal. The received differential signal comprises first and second received voltages, and the differential envelope detector provides a differential output voltage comprising first and second output voltages, where the difference of the first and second output voltages is indicative of the envelope of the difference of the first and second received voltages. For full-wave rectification, the first received voltage is coupled to the non-inverting input port of a first differential amplifier and the inverting input port of a second differential amplifier, and the second received voltage is coupled to the inverting input port of the first differential amplifier and the non-inverting input port of the second differential amplifier. The output ports of the differential amplifiers are coupled to their input ports to provide negative feedback. The output ports of the differential amplifiers source and sink small-signal current to and from capacitors, where the voltage potential of the capacitors provides the first and second output voltages.

Differential envelope detector

A differential-input, differential-output CMOS amplifier having a first differential pair with a first transistor folded with a first cascode transistor, and a second differential pair with a first transistor folded with a second cascode transistor, and having a first auxiliary amplifier to provide negative feedback to the first and second cascode transistors to boost amplifier gain, where the first and second cascode transistors have gates at the same potential. The first differential pair has a second transistor folded with a third cascode transistor, and the second differential pair has a second transistor folded with a fourth cascode transistor, where a second auxiliary amplifier provides negative feedback to the third and fourth cascode transistors to boost amplifier gain, where the third and fourth cascode transistors have gates at the same potential.

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Jerusalem, Israel

Yoel Krupnik