Nuvoton Technology Corporation

Winbond Electronics Corporation

Yoel Hayon

Ziv Hershman

Moshe Alon

Victor Adrian Flachs

Joram Peer

Natan Keren

Natan Keiren

An Integrated Circuit (IC) includes a non-volatile memory (NVM) and secure power-up circuitry. The NVM is configured to store an operational state of the IC. The secure power-up circuitry is configured to (i) during a power-up sequence of the IC, perform a first readout of the operational state from the NVM while a supply voltage of the IC is within a first voltage range, (ii) if the operational state read from the NVM in the first readout is a state that permits access to a sensitive resource of the IC, verify that the supply voltage is within a second voltage range, more stringent than the first voltage range, and then perform a second readout of the operational state from the NVM, and (iii) initiate a responsive action in response to a discrepancy between the operational states read from the NVM in the first readout and in the second readout.

Integrity verification of lifecycle-state memory using multi-threshold supply voltage detection

A security device includes a bus interface and circuitry. The bus interface is coupled to a bus connecting between a host device and a peripheral device. The circuitry is configured to receive, via the bus interface, a clock signal of the bus, and to produce a delayed clock signal relative to the clock signal. The circuitry is further configured to monitor, using the clock signal, transactions communicated between the host device and the peripheral device, in response to identifying a given transaction, of which a portion is expected to be delayed by a predefined time delay relative to the clock signal, to sample the portion of the given transaction using the delayed clock signal, and in response to identifying, based on the sampled portion, that the given transaction violates a security policy, to apply a security action.

Secured communication by monitoring bus transactions using selectively delayed clock signal

A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device. The processor is connected to the bus in addition to the peripheral devices, and is configured to hold a definition that distinguishes between authorized and unauthorized transactions with the memory device, to identify on the bus a transaction in which a bus-master device attempts to access the memory device, and to initiate a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.

Security monitoring of SPI flash

An Integrated circuit (IC) device accommodating a circuit and associated control module, being operative to determine an apparatus characteristic in accordance with one out of few selectable characteristics. The circuit is operative in conjunction with more than three of a plurality of external passive circuits corresponding to the plurality of apparatus characteristics, and includes (N&#x2265;1) digital I/O pins. The control module is operative to: (i) in response to a series of triggering signals, generate samples of the digital I/O pin's state that correspond to a plurality of different sequences of states when each of the plurality of external circuits is respectively applied to the pin and (ii) determining, from the samples, which of the plurality of different sequences of states has occurred that corresponds to the individual external circuit that has been applied to the pin; and (iii) determining an individual apparatus characteristic which corresponds to the determined sequence.

Fully-digital multiple pin value detector apparatus and sampling methods useful in conjunction therewith

A method for capturing images includes associating the pixels with tiles. An input data sequence representing respective current values of the pixels of a currently-captured image frame is accepted. Within each of at least some of the tiles, the current values are compared with respective reference values of the pixels of a reference frame stored in a frame buffer in order to detect variations between the current and reference values. When a variation is detected at a given pixel, the current value is written into the frame buffer in place of a corresponding reference value, and the tile is marked as a changed tile. Subsequent pixel values belonging to the changed tile are written into the frame buffer without comparing the current values of the subsequent pixels to the respective reference values, thereby replacing the reference frame with the currently-captured image frame.

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Givatayim, Israel

Yoel Hayon