Intel Corporation

Yoav Zach

Boris Ginzburg

Eliezer Weissmann

Ronny Ronen

Karthikeyan Karthik Vaithianathan

Ilya Osadchiy

Michael Mishaeli

Robert L Farrell

Esfirush Natanzon

Ido Ouziel

Baruch Chaikin

Esfir Natanzon

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Apparatus and method for accelerating operations in a processor which uses shared virtual memory

Embodiments of systems, apparatuses, and methods for remote action handling are describe. In an embodiment, a hardware apparatus comprises: a first register to store a memory address of a payload corresponding to an action to be performed associated with a remote action request (RAR) interrupt, a second register to store a memory address of an action list accessible by a plurality of processors, and a remote action handler circuit to identify a received RAR interrupt, perform an action of the received RAR interrupt, and signal acknowledgment to an initiating processor upon completion of the action.

Hardware mechanism for performing atomic actions on remote processors

A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

CPU/GPU synchronization mechanism

Growing community of inventors

Karkur, Israel

Yoav Zach