Verisity, Ltd.

Cadence Design (israel) II Ltd.

Yoav Z Hollander

Yaron Kashai

Lev Plotnikov

A system and method for generalized scenarios, for automatically generating tests. The tests are generated from some underlying structure, such as one or more scenarios. The scenarios preferably include a plurality of constraints for generating a test program for generating input values to the test generation process. The scenarios provide a more generalized method for generating tests.

Method and system for automatically creating tests

Method, apparatus, and computer readable medium for functionally verifying a physical device under test (DUT) is described. In one example, verification test data is generated for the physical DUT using a constraint-based random test generation process. For example, the architecture, structure, and/or content of the verification test data may be defined in response to constraint data and an input/output data model. A first portion of the verification test data is applied to the physical DUT. Output data is captured from the physical DUT in response to application of the first portion of the verification test data. A second portion of the verification test data is selected in response to the output data. Expected output data for the physical DUT associated with the verification test data may be generated and compared with the output data captured from the DUT to functionally verify the design of the DUT.

Method and apparatus for functionally verifying a physical device under test

A system and method for testing the quality of a simulation model for the DUT (device under test) through temporal coverage of the testing and verification process. Temporal coverage examines the behavior of selected variables over time, according to a triggering event. Such a triggering event could be determined according to predefined sampling times and/or according to the behavior of another variable, for example. This information is collected during the testing/verification process, and is then analyzed in order to determine the behavior of these variables, as well as the quality of the simulation model for the DUT. For example, the temporal coverage information can be analyzed to search for a coverage hole, indicated by the absence of a particular value from a family of values.

System and method for measuring temporal coverage detection

A method and apparatus are provided for functionally verifying an integrated circuit design. A hardware-oriented verification-specific object-oriented programming language is used to construct and customize verification tests. The language is extensible, and shaped to provide elements for stimulating and observing hardware device models. The invention is platform and simulator-independent, and is adapted for integration with Verilog, VHDL, and C functions. A modular system environment ensures interaction with any simulator through a unified system interface that supports multiple external types. A test generator module automatically creates verification tests from a functional description. A test suite can include any combination of statically and dynamically-generated tests. Directed generation constrains generated tests to specific functionalities. Test parameters are varied at any point during generation and random stability is supported. A checking module can perform any combination of static and dynamic checks. Incremental testing permits gradual development of test suites throughout the design development process. Customized reports of functional coverage statistics and cross coverage reports can be generated. A graphical user interface facilitates the debugging process. High-Level Verification Automation facilities, such as the ability to split and layer architecture and test files, are supported. Both verification environments and test suites can be reused.

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Qiriat Ono, Israel

Yoav Z Hollander