Infineon Technologies LLC

Cypress Semiconductor Corporation

Infinite Memory Ltd.

Spansion Llc.

Infinte Mormories Ltd.

Yoav Yogev

Amichai Givant

Yair Sofer

Shivananda Shetty

Eli Lusky

Stephan Rosner

Hans Van Antwerpen

Ilan Bloom

Steven Walter Wilson

Pawan Kishore Singh

Amir Rochman

Sandeep Krishnegowda

Amit Shefi

Yi He

Cliff Zitlaw

Clifford Alan Zitlaw

Stefano Amato

Itzic Cohen

Idan Koren

Amir Gabai

Systems, methods, and devices prevent data loss in memory devices. Systems may include a non-volatile memory device that includes a first data unit configured to store data for the non-volatile memory device and associated metadata, and a second data unit configured to store data for the non-volatile memory device and associated metadata, wherein the first data unit and second data unit are configured to alternate storing a most recent version of the data and associated metadata. The systems may also include control circuitry configured to read metadata from the first data unit and the second data unit, identify the first data unit as an inactive data unit based on contents of the first data unit and the second data unit, and perform one or more update operations such that the first data unit is updated and set as an active unit when the update operations are complete.

Data loss protection for memory systems and devices

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

One-time programmable (ROTP) NVM

Systems, methods, and devices implement counters with fault tolerance and power loss protection. Systems include a non-volatile memory device that includes a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing an initiation and a completion of each erase operation performed on the first counter. Systems also include control circuitry configured to generate a count value based on a current counter value of the first counter, a current counter value of the second counter, and at least one physical parameter of the first counter.

Continuous monotonic counter for memory devices

Systems, methods, and devices include counters configured to implement count operations. Systems include non-volatile memory devices which include a first counter configured to store a first plurality of data values representing a plurality of count operations, and a second counter configured to store a second plurality of data values representing a number of erase operations applied to the first counter. Systems further include control circuitry configured to implement read, write, and erase operations for the first counter and the second counter, determine a partial count value based, at least in part, on a current value of the second counter and at least one physical parameter of the first counter, and generate a count value by adding the partial count value with a current value of the first counter. Such counters and control circuitry are immune data loss due to power loss events.

A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Nonvolatile memory device with regions having separately programmable secure access features and related methods and systems

A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells: a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in the memory cell array.

Restoring ECC syndrome in non-volatile memory devices

The invention provides a method of managing bad block in a data storage device having an OTP memory die in order to present a continues address space toward the user, by using some of the OTP memory space for the management and maintaining address replacement table. Fast and efficient programming and reading algorithms are presented.

Continuous address space in non-volatile-memories (NVM) using efficient management methods for array deficiencies

OTP Data storage die and device consisting of novel OTP (One-Time-Programming) NVM (Non-Volatile-Memory) die is disclosed. The OTP Data storage device can be used in typical host applications with standard interface protocols and file system. The novel OTP memory is a dual memory with both RAM (random access memory) capability and NAND Flash like interface. These features enable to achieve efficient management capabilities and dense array for the OTP data storage device.

Non-volatile dual memory die for data storage devices

The invention provides a method of managing data updates in DOS-based data storage device having an OTP memory die that includes a code region having a first memory capacity and a code region access resolution and a data region having a second memory capacity and a data region access resolution. The second memory capacity is larger than the first memory capacity and the code region access resolution is finer than the data region access resolution. The method includes chronologically writing a log entry in the code region indicating the change in FAT and root directory for each change in user data written in the data region.

Growing community of inventors

Mazkeret Batya, Israel

Yoav Yogev