Freescale Semiconductor,inc.

Nxp Usa, Inc.

Bar-ilan University

Birad-research & Development Company Ltd.

Birad—research & Development Corapany Ltd.

Yoav Weizman

Shai Shperber

Joseph Shor

Alexander Fish

Robert Giterman

Osnat Keren

Lior Aviv

Michael Priel

Anton Rozen

Sergey Sofer

Leonid Fleshel

Adam Teman

Ezra Baruch

Yehim-Haim Fefer

Roi Levi

Yefim-Haim Fefer

Itamar Levi

Yitzhak Elhanan Schifmann

Mikhail Bourgart

Matan Elkoni

Segey Sofer

Maoz Vizentovski

Jacob Fridburg

A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.

Secured memory

A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

Information redistribution to reduce side channel leakage

A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.

Detecting unreliable bits in transistor circuitry

A method uses data retention time (DRT) characteristics of a logic-compatible gain-cell embedded DRAM (dynamic random-access memory) (GC-eDRAM) array in a transistor circuit as a source for physical unclonable function (PUF) signature extraction of the circuit.

Dynamic memory physical unclonable function

A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.

Physical unclonable functions related to inverter trip points

A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.

Semiconductor device arrangement, a method of analysing a performance of a functional circuit on a semiconductor device and a device analysis system

A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

Method of detecting irregular current flow in an integrated circuit device and apparatus therefor

A method for evaluating temperature is disclosed. The method includes setting a configuration of a configurable delay line out of multiple possible configurations, and delaying a first input signal by a temperature sensitive delay line, delaying a second input signal by the configurable delay line. The configurable delay line is less sensitive to temperature than the temperature sensitive delay line. The method also includes detecting, by a phase detector, a delay difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line, repeating the setting, delaying of the first input signal, delaying of the second input signal and detecting, until the delay difference is below a threshold, and evaluating the temperature of the temperature sensitive delay line in response to a configuration of the configurable delay line that results in the delay difference that is below the threshold.

Device and method for evaluating a temperature

A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.

Method for testing a variable digital delay line and a device having variable digital delay line testing capabilities

A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.

Method for testing noise immunity of an integrated circuit and a device having noise immunity testing capabilities

A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the configurable delay line that introduces a delay that substantially equals a delay introduced by the temperature sensitive delay line; and (b) determine a temperature of the temperature sensitive delay line in response to the found configuration.

A system () for testing and failure analysis of an integrated circuit () is provided using failure analysis tools (). An analysis module () having a number of submodule test structures is incorporated into the integrated circuit design. The test structures are chosen in dependence upon the failure analysis tools () to be used. The rest of the integrated circuit contains function modules () arranged to provide normal operating functions. By analysing the submodule test structures of the analysis module () using the failure analysis tools (), physical parameters of the integrated circuit () are obtained and used in subsequent testing of the function modules () by the failure analysis tools (), thus simplifying the testing of the integrated circuit () and reducing the time taken to perform a failure analysis procedure.

Growing community of inventors

Kfar-Vitkin, Israel

Yoav Weizman