Samsung Electronics Co., Ltd.

Tower Semiconductor Ltd.

Digitaloptics Corporation International

3G. Com, Inc.

Infineon Technologies Ag

National Semiconductor Corporation

Zikbit Ltd.

Samsung Semiconductor Israel R&d Center (Sirc)

Simulog, Inc.

Lantiq Deutschland Gmbh

Yoav Lavi

Uri Kinrot

Eugene Fainstain

Miriam Fraenkel

Anatoly Litvinov

Shlomo Polonsky

Avidan Akerib

Eli Ehrman

Alex Alon

Oleg Dadashev

Irina Alon

Ishai Nachumovsky

Haim Granot

Mickey Bahar

Alon Boner

Meny Yanni

Rivka Blum

David Drori

Elchanan Rappaport

Robert Knuth

Amnon Rom

Anat Hershko

Georgiy Shenderovitch

Eran Weingatren

Elliot Cohen

Amnon c/o IC Com Rom

Georgy Shenderovitch

Imaging apparatus () is provided for use with an image sensor (). The apparatus includes a non-linear mapping circuit (), which is configured to receive a raw stream of input pixel values generated by the image sensor and to perform a non-linear mapping of the input pixel values. to generate a mapped stream of mapped pixel values, and a linear convolution filter (), which is arranged to filter the mapped stream of mapped pixel values to generate a filtered stream of filtered pixel values. Other embodiments are also described.

Non-linear transformations for enhancement of images

A method for imaging includes receiving an input image that includes a matrix of pixels () having input pixel values. The input pixel values are processed so as to detect a region of saturation in the input image. A first image filtering operation is applied to the input pixel values of at least the pixels that are outside the region of saturation, so as to generate first filtered pixel values. A second image filtering operation is applied to the input pixel values of at least the pixels that are within the region of saturation, so as to generate second filtered pixel value. An enhanced output image is generated by stitching together the first and second filtered pixel values.

Image restoration with enhanced filtering

An image enhancement circuit () includes an input interface (), which is operative to accept a stream of input pixel values belonging to pixels () of an input image. The input image includes a plurality of different input sub-images including respective subsets of the pixels, such that the input pixel values of the pixels in the different input sub-images are interleaved in the stream. A plurality of filter cells () are connected in a two-dimensional array configuration and are arranged to separately filter the input pixel values of each of the input sub-images with respective two-dimensional deconvolution kernels so as produce respective output sub-images that include output pixel values. A multiplexer () is coupled to multiplex together the output pixel values of the output sub-images so as to produce a filtered output image.

Image enhancement using hardware-based deconvolution

Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).

Processor arrays made of standard memory cells

Various embodiments of the invention comprise imaging systems and methods for an interlaced scan of an image sensor array. An exemplary method is described in which an image sensor array is exposed to light for a period of time to generate voltage levels representative of array pixels. The voltage levels of a first field of the array are scanned, the first field comprising a number of row-pairs of the array. The voltage levels of a second field of the array are also scanned, the second field comprising a different set of row-pairs interlaced with the row-pairs of the first field. A set of image data from the first field and a set from the second field are generated. Various row-pairs may be averaged in generating the sets of image data. Additionally, exemplary imaging systems are described with various configurations for scanning an image sensor array in interlaced mode.

Better SNR ratio for downsized images using interlaced mode

Methods and apparatus to measure small shifts and rotations of video images captured in short succession after a first reference video image is captured, and to add the sequence of captures while shifting or rotating back the shifted or rotated images, in order to improve the SNR in low light conditions.

Smear correction in a digital camera

A method of compressing an image according to an image compression algorithm includes sequentially receiving pixel values into a buffers bank in line-by-line order. The image includes a plurality of pixels arranged into lines and columns. Each pixel has a pixel value associated therewith. Each line has L pixels. The image compression algorithm operates on blocks of pixels, each block having N lines and M columns. The method also includes storing each block-line of pixel values in a buffer of the buffers bank. A block-line includes M consecutive pixels of a line. The method also includes, for each block-line, storing a pointer to the buffer in which the block-line is stored and reading block-lines out of the buffers bank to a compression engine, wherein the block-lines are read out of the buffers bank in an order that is different from the line-by-line order in which the block-lines were received into the buffers bank. The method further includes compressing the image according to the image compression algorithm and displaying the image.

Reduced buffer size for JPEG encoding

Embodiments of the current invention provide for systems and methods for correcting shading effects in image sensors. More specifically, but not by way of limitation, embodiments of the current invention provide methods and systems for dynamically correcting shading effects for digitally converted outputs from individual pixels on a pixel array in the image sensor, wherein the shading correction may be calculated according to a function of an elliptical-type equation from the radial location of the pixel on the pixel array. In embodiments of the present invention, the correction is performed at the Bayer domain before demosaicing processing to provide for accuracy of shading correction and low power consumption.

Methods and systems for anti shading correction in image sensors

Embodiments of the present invention relate in general to systems and methods for dynamically correcting color cross-talk and related color distortion in an image sensor. More specifically, but not by way of limitation, certain embodiments of the present invention relate to correcting pixel outputs from a pixel array in an image sensor at the Bayer domain for color cross-talk and/or green disparity using hyperbolically varying correction functions to dynamically derive color cross-talk correction factors using pixel location on the pixel array, a selected pixel output and related outputs from neighboring pixels on the image sensor prior to or synchronous with color interpolation.

Systems and methods for correcting green disparity in imager sensors

A system and method for improving error detection and correction for transmitted data. An iterative error detection method is used to determine a relative likelihood that decoded data is an accurate representation of the original data. An independent error correction unit operates on the decoded data and a result from the independent error correction unit is injected into the iterative error detection method to improve the reliability of the error detection method.

Mechanism for turbo decoding when CRC for partial blocks is provided

A correlator circuit for calculating the correlation between a signal sequence and a binary reference sequence. A unique method of calculating the correlation value between the two sequences provides for the reduction in necessary computations and, as a result, a reduction in the amount of time expended in calculating the correlation is realized.

Simplified circuit for correlating binary and non-binary sequences

A method for executing instructions in a data processor and improvements to data processor design, which combine the advantages of regular processor architecture and Very Long Instruction Word architecture to increase execution speed and ease of programming, while reducing power consumption. Instructions each consisting of a number of operations to be performed in parallel are defined by the programmer, and their corresponding execution unit controls are generated at compile time and loaded prior to program execution into a dedicated array in processor memory. Subsequently, the programmer invokes reference instructions to call these defined instructions, and passes parameters from regular instructions in program memory. As the regular instructions propogate down the processor's pipeline, they are replaced by the appropriate controls fetched from the dedicated array in processor memory, which then go directly to the execution unit for execution. These instructions may be redefined while the program is running. In this way the processor benefits from the speed of parallel processing without the chip area and power consumption overhead of a wide program memory bus and multiple instruction decoders. A simple syntax for defining instructions, similar to that of the C programming language is presented.

Configurable long instruction word architecture and instruction set

A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value. Then, the bit to be shifted into the shift register is compared with the bit to be shifted out of the shift register. The output signal of the sequential logic device is toggled if no match is detected, and maintained if a match is detected. In other embodiments, functions other than an exclusive OR function can be implemented.

Implementation of functions of multiple successive bits of a shift register

Five architectures for the implementation of virtual ground non-volatile content-addressable memory are provided. Three of the architectures are applicable to 2-bit non-volatile memory transistors having separate programming capability for two current directions (i.e., drain-to-source and source-to-drain. Another architecture is applicable to any floating gate memory transistor, including 1-bit and 2-bit non-volatile memory transistors. In general, an array of non-volatile memory transistors is arranged in a plurality of horizontal rows and vertical columns. Words are stored in selected columns of the array. Horizontal compare lines are coupled to receive a comparand word, with each compare line being coupled to the gates of the memory transistors in a row of the array. The vertically aligned source/drain regions of the memory transistors are coupled to form word lines. Sense amplifiers are coupled to selected word lines. Switches can be coupled to the sense amplifiers and/or word lines, thereby enabling program and compare operations to be performed in two different directions when 2-bit non-volatile memory transistors are used. Compare operations can be performed over two or more phases when 2-bit non-volatile memory transistors are used. Sequential logic circuits can also be coupled to the sense amplifiers, and used to store the results of different compare phases.

Content-addressable memory for virtual ground flash architectures

A structure and method for implementing an EEPROM using 2-bit non-volatile memory cells. Each memory cell has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. The memory cells are arranged in one or more rows, with a word line coupling the gates of all of the memory cells in each row. Diffusion bit lines couple the first charge trapping region of each memory cell with the second charge trapping region of an adjacent memory cell. When the first charge trapping region of a memory cell is erased, the second charge trapping region of the adjacent memory cell is incidentally erased. This incidental erasure is effectively avoided by: (1) reading the bit stored in the second charge trapping region, (2) writing this bit to a storage device, (3) performing the erase operation, and then (4) restoring the bit from the storage device to the second charge trapping region of the adjacent memory cell. If an erase operation results in the incidental erasure of additional bits (as will occur when more than one row of memory cells is coupled to a single diffusion bit line), then all of the bits that would be incidentally erased are written to the storage device before the erase operation, and are restored to the array after the erase operation. The incidental erasure can also be rendered moot by using only one charge trapping region of each memory cell.

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Raanana, Israel

Yoav Lavi