Cadence Design Systems, Inc.

Yoav Hollander

Yael Kinderman

Efrat Gavish

Matan Vax

Ohad Givaty

Vitaly Lagoon

Yael Feldman

Reshef Meir

Embodiments provide methods, systems, and devices involving transaction correlation tools that may record a limited number of run attributes yet are likely to be important in the debugging process. Some embodiments may include novel tabular representations of the runs. Embodiments may allow the user to specify directives for the recording of the runs and the creation of these tables. Embodiments may include comparing sets of failing and passing runs, which may be generated at random. This approach is called statistical debugging, as it employs statistical tools to find attributes of the DVE that tend to co-occur with the failure.

Transaction correlation system

A method and system are provided for automatically generating executable system-level tests from an initial action or partially specified scenario by accumulating necessary complement actions and forming a set of constraints required by the initial action and the necessary complement actions. The set of constraints is solved by a constraint solving engine to provide an at least partial sequence of the actions and parameters thereto that satisfies the set of constraints. The sequence of actions that comply with the set of constraints are used to generate an executable system-level test code.

Systems and methods for automatically generating executable system level-tests from a partially specified scenario

A computerized method of characterizing a DUV includes executing in a verification environment (VE) a set of verification tests to stimulate the DUV to collect test results from the DUV. The method further includes collecting a set of failure data for the test results; and generating sets of common failures based on clusters of features of interest in the set of failure data. The method further includes generating a set of hints from the common failures; wherein the hints indicate a potential failure mode or a potential root cause failure of the DUV for the test results for the simplified set of tests; and generating a set of debug data from the clusters of features of interest. The method further includes transferring the set of hints and the set of debug data to a user computer for storage, display, and use in an interactive debug session of the DUV.

Automatic debug apparatus and method for automatic debug of an integrated circuit design

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Kiryat-Ono, Israel

Yoav Hollander