Speedata Ltd.

Technion Research & Development Foundation Limited

Yoav Etsion

Dani Voitsechov

Rafi Shalom

Jonathan Friedmann

Evgeni Krimer

Yonatan Gottesman

Lluis Vilanova

A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to configure at least some of the compute nodes and interconnects in the compute fabric to execute specified code instructions, and to send to the compute fabric multiple threads that each executes the specified code instructions. A compute node among the compute nodes is configured to execute a code instruction for a first thread, and to transfer a result of the code instruction within the fabric, for use as an operand by a second thread, different from the first thread.

Inter-thread communication within the compute fabric of a multi-threaded reconfigurable coarse-grain array without accessing system memory

A hardware-implemented file reader includes an interface, multiple hardware-implemented column readers and a hardware-implemented record reconstructor. The interface is configured to access a file including multiple records. The records store values in accordance with a nested structure that supports optional values and repeated values. The file is stored in a columnar format having multiple columns, each column storing (i) compressed values and (ii) corresponding compressed structure information that associates the values in the column to the nested structure of the records. Each column reader is configured to be assigned to a respective selected column, and to read and decompress both the values and the structure information from at least a portion of the selected column. The record reconstructor is configured to reconstruct one or more of the records from at least portions of the columns that are read by the column readers, and to output the reconstructed records.

Hardware-implemented file reader

Inter-thread communication in multi-threaded reconfigurable coarse-grain arrays

A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive a software program represented as a set of interconnected Data-Flow Graphs (DFGs), each DFG specifying code instructions that perform a respective portion of the software program, to schedule execution of the DFGs in time alternation, and, for each DFG being scheduled, to configure at least some of the compute nodes and interconnects in the compute fabric to execute the code instructions specified in the DFG, and send to the compute fabric multiple threads that each executes the code instructions specified in the DFG.

Handling multiple graphs, contexts and programs in a coarse-grain reconfigurable array processor

A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.

Coarse-grain reconfigurable array processor with concurrent handling of multiple graphs on a single grid

A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.

Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware

Data access in a storage device managed by a storage controller is carried out by receiving in the storage controller offsets in objects directly from a plurality of requesting entities of a computer system. The computer controls a mapping mechanism operated by the storage controller, wherein the mapping mechanism relates the offsets in the objects into physical addresses of the data on the storage device, and wherein the data is accessed at the physical addresses.

Growing community of inventors

Atlit, Israel

Yoav Etsion