Intel Corporation

Yoav Almog

Roni Rosner

Hong Wang

Stephan Jourdan

Ronny Ronen

Milind Baburao Girkar

Wei Ey Li

Ron Gabor

John Thomas Shen

Lihu Rappoport

Perry H Wang

Xinmin Tian

Ido Ouziel

Gerolf F Hoflehner

Franck Sala

Bob Valentine

Satish Narayanasamy

Amir Leibovitz

Daniel LaVery

Naftali Schwartz

Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.

Efficient method and apparatus for employing a micro-op cache in a processor

An optimization unit to search for two or more candidate instructions in an instruction trace and to merge the two or more candidate instructions into a single instruction with multiple data (SIMD) according to a depth of a trace dependency and a common operation code of the two or more candidate instructions.

Method and apparatus to vectorize multiple input instructions

Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is adapted to accommodate a size of the dependency chains; and/or processing in parallel a plurality of dependency chains of a trace. Other embodiments are described and claimed.

System, method and apparatus for dependency chain processing

Growing community of inventors

Haifa, Israel

Yoav Almog