United Microelectronics Corp.

Yo-Yi Gong

Tien-Jui Liu

Le-Tien Jung

Chuck Chen

A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each connection portion connects to one end of the conductive line and surrounds a contact region. The spacers are disposed at the edge of the closed loop to cover the substrate between the conductive lines. The first doping regions are located in the substrate outside the closed loop and the spacers. The second doping regions are located in the substrate under the spacers. The contacts are electrically connected to the first doping regions within the contact regions. Because the spacers and the conductive lines are incorporated into a test key structure, the influence of spacers upon the entire device can be more accurately determined.

Test key structure

The invention relates to a method of forming a stack-gate of a non-volatile memory. In this method, the stack-gate is formed in a predetermined region of the substrate of a semiconductor wafer. Then, a gate oxide layer, a first gate conductive layer, a dielectric layer, and a passivation layer are formed followed by lithography and stripping of the photo-resist layer and removal of the passivation layer from the dielectric layer. Finally, a second gate conductive layer is formed on the dielectric layer as the control gate of the stack-gate. The passivation layer can prevent the dielectric layer from being damaged during stripping of the photo-resist layer.

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Hsinchu, Taiwan

Yo-Yi Gong