Skhynix Inc.

Yo-Sep Lee

Choung-Ki Song

Choung Ki Song

Chang-Hyun Kim

Jung-Hyun Kim

Dong-Ha Lee

Seon-Woo Hwang

A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.

Stacked semiconductor device and semiconductor system including the same

A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.

Stacked semiconductor device and test method thereof

A memory includes: first to Nareas refreshed based on first to Nrefresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nrefresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nrefresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nrefresh control signals, based on the Nrefresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.

Memory performing refresh operation and operation method of the same

A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.

Delay circuit

A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information.

Memory device and memory system including the same

A memory includes a plurality of word lines, a target address generation unit generating one or more target addresses by using a stored address, a refresh control section activating a refresh signal in response to a refresh command that is periodically inputted and periodically activating the refresh signal in a self-refresh mode, a target refresh control section activating a target refresh signal when the refresh signal is activated M times, wherein the M is a natural number, and deactivating the target refresh signal in the self-refresh mode, and a row control section sequentially refresh a plurality of first word lines in response to the refresh signal and refreshing a second word line corresponding to the target address in response to the refresh signal when the target refresh signal is activated.

Memory and memory system for periodic targeted refresh

A semiconductor memory device includes a plurality of word lines each of which are connected to a plurality of memory cells, a row control unit suitable for sequentially activating and precharging a word line corresponding to a target address and a predetermined (N) number of adjacent word lines during a target activation mode, and a mode exit control unit suitable for counting the number of activation operations by the row control unit during the target activation mode to determine whether or not to exit from the target activation mode.

Semiconductor memory device and memory system including the same

A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.

Memory, memory system including the same and method for operating memory

A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.

Semiconductor memory device capable of selectively enabling/disabling a first input unit and a second input unit in response to a first and second internal clock in a gear-down mode

A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.

Memory device and memory system having programmable refresh methods

A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.

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Gyeonggi-do, South Korea

Yo-Sep Lee