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Hygon Information Technology Co., Ltd.

Arcadia Innovation Incorporated

Yizhou Lin

Hongchang Liang

Jian Tang

A method of time budgeting an integrated circuit (IC) that includes determining an initial value of time delay variables for each block of a plurality of blocks along a set of timing paths based on delays of each design module of the blocks and determining a value of at least one advanced timing factor adjusting a clock period of the IC along each timing path. The method then generates a time budget for ports along each timing path based on the value of the at least one advanced timing factor and the initial value of the time delay variable. The method then optimizes the value of time delay variables by calculating new values of the time delay variables that satisfy each timing path to minimize a possibility of timing violations and to satisfy the clock period of the IC, which is adjusted by the value of the advanced timing factor.

Method to reduce full-chip timing violation through time budgeting in integrated circuit design

A method of time budgeting an integrated circuit (IC) including acquiring a graph data structure and clock cycle requirements, where the graph data structure includes at least two identical blocks of a plurality of blocks that correspond to an identical design module. The method acquires internal and external delay values ports of each design module, and sets parameters, which include the internal and external delay values of the at least two identical blocks as equivalent for the identical blocks. The method performs optimization of the parameters of the ports of all of the blocks, and determines whether the optimized parameters of each of the ports satisfy predetermined requirements of the IC. The method outputs a final design of the IC design based on results of the optimization for manufacturing of the IC based on the final design.

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Santa Clara, CA, United States of America

Yizhou Lin