Chengdu Boe Optoelectronics Technology Co., Ltd.

Boe Technology Group Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Yixuan Long

Yi Zhang

Xiaoqing Shu

Biao Liu

Tingliang Liu

Huijuan Yang

Tinghua Shang

Xiangdan Dong

Hongwei Ma

Peng Xu

Mengmeng Du

Siyu Wang

Maoying Liao

Yujing Li

Lingtong Li

Liheng Wei

Jiaxing Chen

Nanhao Chen

Zuoji Niu

Yang Zhou

Chang Luo

Jianchang Cai

Jiangtao Deng

A display substrate and a display apparatus are provided, wherein the display substrate includes: a base substrate and a drive structure layer provided on the base substrate, the drive structure layer includes pixel circuits arranged in an array, the pixel circuits arranged in an array includes a plurality of power supply lines; the pixel circuit further includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate; the plurality of power supply lines include a plurality of first power connection lines disposed in a first conductive layer and a plurality of second power connection lines disposed in a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, the first power connection line and the second power connection line extend in a first direction.

Display substrate and display apparatus

An array substrate is provided. The array substrate includes a plurality of first type data lines and a plurality of second type data lines. A respective one of the plurality of first type data lines crosses over subpixel apertures of multiple subpixels of a first color, and does not crosses over subpixel apertures of any subpixel of a second color and does not crosses over subpixel apertures of any subpixel of a third color, the first color, the second color, and the third color being different colors. A respective one of the plurality of second type data line does not cross over any subpixel aperture. A respective subpixel aperture of a subpixel of the first color includes a first region and a second region. A ratio of a first area of the first region to a second area of the second region is in a range of 2:8 to 8:2.

Array substrate and display apparatus

A display substrate is provided, and the display substrate includes a first display region, a second display region and a transitional display region; the first display region includes a plurality of first sub-pixels, each first sub-pixel (P) includes a first light-emitting device; the second display region includes a plurality of first pixel driving circuit and a plurality of first transition pixel driving circuits, the plurality of first pixel driving circuits are electrically connected to first light-emitting devices respectively through a plurality of first wires; the transition display region is between the first display region and the second display region, including a first transition sub-region and a second transition sub-region, a plurality of first transition light-emitting devices in the first transition sub-region are electrically connected to the plurality of first pixel driving circuits respectively through a plurality of second wires, the second transition sub-region includes a plurality of second transition sub-pixels.

Display substrate

Provided is a pixel circuit configured to drive, in an Xframe period, a light emitting device to emit light. The Xframe period includes Y data writing stages and Z light emitting stages, in which a ydata writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y≤Y, and Y>Z.

Pixel circuit, method of driving pixel circuit, display panel, and display device

A driving backplane, a display panel and a display device are provided. The driving backplane has a pixel circuit, a data line and a power line; transistors include a driving transistor, a writing transistor, a compensation transistor and an initialization transistor; the power line includes a power line body extending along a column direction and a shielding part connected to a side of the power line body along a row direction; at least a portion of the writing transistor and the initialization transistor are located between the power line and the data line; a channel of the driving transistor overlaps with the power line; and a channel of the compensation transistor overlaps with the shielding part.

Driving backplane, display panel and display device

An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective voltage supply line, connected to a first capacitor electrode and a semiconductor material layer. An orthographic projection of a first anode on a base substrate at least partially overlaps with an orthographic projection of a node connecting line in a respective first subpixel. An orthographic projection of a second anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective second subpixel. An orthographic projection of a third anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective third subpixel. An orthographic projection of a fourth anode on the base substrate at least partially overlaps with an orthographic projection of the node connecting line in a respective fourth subpixel.

Provided is a pixel circuit configured to drive, in an Xframe period, a light emitting device to emit light. The Xframe period includes Y data writing stages and Z light emitting stages, in which a ydata writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y≤Y, and Y≥Z.

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Yixuan Long