Applied Materials, Inc.

Yixiong Yang

Srinivas Gandikota

Jacqueline S Wrench

Wei V Tang

Steven C H Hung

Seshadri Ganguli

Shih Chung Chen

Lin Dong

Yongjing Lin

Naomi Yoshida

Yong Yang

Karla M Bernal Ramos

Mandyam Sriram

Guoqiang Jian

Paul F Ma

Yong Wu

Wenyi Liu

Luping Li

Dien-Yeh Wu

Yu Lei

Joung Joo Lee

Yi Xu

Annamalai Lakshmanan

Anqing Cui

Wenyu Zhang

Feihu Wang

Jianqiu Guo

Siddarth A Krishnan

Muhammad M Rasheed

Rongjun Wang

Susmit Singha Roy

Mario Dan Sanchez

Bo Wang

Srinivas D Nemani

Mei Yin Chang

David P Thompson

Wei Liu

Feng Quan Liu

Jeffrey W Anthis

Zhebo Chen

Xinyu Fu

Sang Ho Yu

Sahil Patel

Wen Xiao Chen

Nikolaos Bekiaris

Liqi Wu

Wei Lei

Arkaprava Dan

Steven C Hung

Chi-Chou Lin

Deepak Jadhav

Aixi Zhang

Xingyao Gao

Shiyu Yue

Ju Hyun Oh

Ludovic Godet

Michael Patrick Chudzik

Robert Jan Visser

Avgerinos V Gelatos

Lan Yu

Bo Zheng

Mohith E Verghese

Benjamin Colombeau

Fei C Wang

Prerna Sonthalia Goradia

Kurtis Leschkies

Xin Liu

Xiaoxiong Yuan

Yu Wen Chang

Kazuya Daito

Xiangjin Xie

Atashi Basu

Vikash Banthia

Xiaodong Wang

Geetika Bajaj

Sang-Ho Yu

Kevin Kashefi

Ashutosh Agarwal

Tsung-Han Yang

David Michael Thompson

Cong Trinh

Faruk Gungor

Pradeep Subrahmanyan

Bhushan N Zope

Yifei Wang

William Kuang

Myungsun Kim

Chih-Hsun Hsu

Darshan Thakare

Gang Shen

Jose Alexandro Romero

Jiajie Cen

Zhimin Qi

In Seok Hwang

Srividya Natarajan

Kunal Bhatnagar

Drew Phillips

Jonathan Robert Bakke

Kyoung-Ho Bu

Conformally deposited molybdenum films having reduced resistivity and methods of forming the same are disclosed. The methods include converting an amorphous silicon layer to a metal layer by thermally soaking the amorphous silicon layer comprising silicon atoms in the presence of a metal compound selected from the group consisting of a molybdenum compound and a tungsten compound until at least a portion of the silicon atoms in the amorphous silicon layer are replaced by metal atoms selected from the group consisting of molybdenum atoms and tungsten atoms. The methods include conformally depositing a molybdenum film on the metal layer.

Conformal molybdenum deposition

A method for forming a metal nitride layer on a substrate includes exposing a substrate having features formed therein to a first deposition gas mixture including metal source material in a processing chamber to deposit metal source material in the features, supplying a first purge gas mixture into the processing chamber to remove excess metal source material and reaction byproducts from the processing chamber, exposing the substrate to a second deposition gas mixture including a nitride source compound in the processing chamber to form no more than one monolayer of metal nitride, supplying a second purge gas mixture into the processing chamber to remove excess nitride source compound and reaction byproducts from the processing chamber, and exposing the substrate to plasma using a microwave plasma source.

Method of tuning film properties of metal nitride using plasma

Methods for depositing a metal contact stack on a substrate are described. The metal stack includes a metal cap layer and a molybdenum conductor layer. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity metal contact stack

A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, wherein the barrier layer is TiN; and forming a metal layer in the feature and over the barrier layer, wherein the metal layer is at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).

Methods and apparatus for seam reduction or elimination

A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl, MoCl) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

Metal oxide preclean for bottom-up gapfill in MEOL and BEOL

Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.

Thermal process chamber lid with backside pumping

A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

One chamber multi-station selective metal removal

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

Liner for V-NAND word line stack

A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.

Metal based hydrogen barrier

A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region.

MOSFET gate engineerinng with dipole films

A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

Threshold voltage modulation for gate-all-around FET architecture

Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

Enhancing gapfill performance of dram word line

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-κ dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-κ dielectric layer on the interfacial layer, and a metal film on the high-κ dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-κ dielectric layer.

Integrated dipole region for transistor

Methods and apparatus for processing a substrate is provided herein. For example, a method for processing a substrate comprises depositing a silicide layer within a feature defined in a layer on a substrate, forming one of a metal liner layer or a metal seed layer atop the silicide layer within the feature via depositing at least one of molybdenum (Mo) or tungsten (W) using physical vapor deposition, and depositing Mo using at least one of chemical vapor deposition or atomic layer deposition atop the at least one of the metal liner layer or the metal seed layer, without vacuum break.

Methods and apparatus for processing a substrate

A sacrificial sealing layer is formed on a high-κ metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-κ metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-κ metal oxide layer to form a dipole region.

Amorphous silicon-based scavenging and sealing EOT

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Fremont, CA, United States of America

Yixiong Yang