Synopsys, Inc.

Yiu-Chung Mang

Vishal Khandelwal

Sanjay Dhar

Kok Kiong Lee

Pei-Hsin Ho

Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.

Concurrent optimization of timing, area, and leakage power

Look-up based fast logic synthesis

A system that determines the timing of an integrated circuit (IC) design is presented. During operation, the system receives a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design. Next, the system estimates capacitances for cells within the IC design based on analytic models of the cells. The system then estimates the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization.

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Toronto, Canada

Yiu-Chung Mang