Novas Software, Inc.

Synopsys, Inc.

Yirng-An Chen

Yu-Chin Hsu

Furshing Tsai

KunMing Ho

Tayung Liu

James Herbert Kukula

Robert F Damiano

Bharat Kalyanpur

Chieh Changfan

Wells Woei-Tzy Jong

Bassam Tabbara

George Bakewell

Scott Sandler

A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using rules that filter out latches that do not exhibit flip flop-like output behavior. Clock modeling is then performed on the remodeled layout. Because the remodeled layout contains fewer latches than the original synthesized layout, the computational expense and time required for clock modeling (and hence, formal verification) on the remodeled layout can be significantly reduced over the requirements for clock modeling (and formal verification) on the original synthesized layout.

Latch modeling technique for formal verification

A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement. Each statement event symbol references the signal whose value is computed by the corresponding statement evaluation and indicates a value of that signal computed when the statement was evaluated. Each statement event symbol also references the other signals having values of which the statement indicates the computed signal value is a function and indicates those other signals values as of the simulation time at which the statement was evaluated.

IC behavior analysis system

A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

System for characterizing simulated circuit logic and behavior

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San Jose, CA, United States of America

Yirng-An Chen