Seagate Technology Incorporated

United States of America As Represented by the Secretary of the Air Force

University of Pittsburgh

Other

Yiran Chen

Hai Li

Xiaobin Wang

Hongyue Liu

Yong Lu

Dimitar Velikov Dimitrov

Wenzhong Zhu

Haiwen Xi

Harry Hongyue Liu

Henry F Huang

Alan Xuguang Wang

Ran Wang

Xiaohua Lou

Yuankai Zheng

Xuguang Alan Wang

Daniel Seymour Reed

Yuan Yan

Olle Gunnar Heinonen

Brian Lee

Zheng Gao

Song Sheng Xue

Andrew John Carter

Rod V Bowman

Kang Yong Kim

Yang Li

Dexin Wang

Dadi Setiadi

Richard W Linderman

Qing Wu

Maroun Khoury

Garrett Rose

Miao Hu

KangYong Kim

Wei Tian

Patrick Joseph Ryan

Kirill A Rivkin

Andreas Karl Roelofs

Jun Zheng

Zheng Li

Wei Tan

Mark D Barnell

Enes Eken

Wujie Wen

Wengzhong Zhu

Xiuyuan Bi

Ismail Bayram

A two-dimensional accessible non-volatile memory apparatus includes an array comprising a plurality of non-volatile memory cells, the array being a crossbar-based non-volatile memory structure, the memory cells being arranged in a plurality of rows and a plurality of columns. The apparatus further includes row read/write circuitry coupled to the array and structured and configured to provide read and write access to the memory cells in any one of the rows on an individual row basis, and column read/write circuitry coupled to the array and structured and configured to provide read and write access to the memory cells in any one of the columns on an individual column basis.

Two-dimensionally accessible non-volatile memory

Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

Data updating in non-volatile memory

A memory device, such as an FeDRAM device, includes a memory array including a plurality of rows, each row having a plurality of storage elements (e.g., FeFETs). The memory device further includes a plurality of refresh trigger circuits, each refresh trigger circuit being associated with a respective one of the rows. Each refresh trigger circuit is structured to produce an output signal indicative of an estimated degradation of a memory window of one or more of the storage elements of the associated one of the rows. The memory device also further includes control circuitry coupled to each of the refresh trigger circuits, wherein the control circuitry is structured and configured to determine whether to initiate a refresh of the storage elements of a particular one of the rows based on the output signal produced by the refresh trigger circuit associated with the particular one of the rows.

Adaptive refreshing and read voltage control scheme for a memory device such as an FeDRAM

Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.

Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems

A method of reading a memory cell of a magneto-resistive random access memory device, wherein the memory cell has a ferromagnetic free layer having a first magnetization orientation and a ferromagnetic reference layer, includes applying a first read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a first voltage generated by the memory cell in response to the first read current, generating a magnetic field adjacent to the memory cell, the magnetic field having a second magnetization orientation that is not parallel to the first magnetization orientation, while the magnetic field is being generated, applying a second read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a second voltage generated by the memory cell in response to the second read current, and determining a state of the memory cell based on the first voltage and the second voltage.

Magnetic-assisted nondestructive self-reference sensing method for spin-transfer torque random access memory

Invention provides an apparatus and method for performing signal processing on a crossbar array of resistive memory devices. The invention is implemented using one or multiple crossbar arrays of resistive memory devices in conjunction with devices for converting input real number representations to voltage waveforms, devices for converting current waveforms into voltage waveforms, and devices for converting voltage waveforms to real numbers outputs.

Method and apparatus for performing signal processing on a crossbar array of resistive memory devices

An apparatus that performs the mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation operations with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture.

Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices

Devices and methods for generating a random number that utilizes a magnetic tunnel junction are disclosed. An AC current source can be in electrical connection to a magnetic tunnel junction to provide an AC current to the magnetic tunnel junction. A read circuit can be used to determine a bit based on a state of the magnetic tunnel junction. A rate of production of the bits can be adjusted, such as by adjusting a frequency or amplitude of the AC current. A probability of obtaining a '0' or '1' bit can be managed, such as by an addition of DC biasing to the AC current.

Random bit generator that applies alternating current (AC) to magnetic tunnel junction to generate a random bit

A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.

Bipolar CMOS select device for resistive sense memory

Various embodiments of the present invention are generally directed to an apparatus and method for non-volatile caching of data in a memory hierarchy of a data storage device. In accordance with some embodiments, a pipeline memory structure is provided to store data for use by a controller. The pipeline has a plurality of hierarchical cache levels each with an associated non-volatile filter cache and a non-volatile victim cache. Data retrieved from each cache level are respectively promoted to the associated non-volatile filter cache. Data replaced in each cache level are respectively demoted to the associated non-volatile victim cache.

Memory hierarchy with non-volatile filter and victim caches

Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.

Non-sequential encoding scheme for multi-level cell (MLC) memory cells

Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

Bit set modes for a resistive sense memory cell array

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Spin-transfer torque memory self-reference read method

Various embodiments of the present invention are generally directed to a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.

Non-volatile resistive sense memory on-chip cache

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Pittsburgh, PA, United States of America

Yiran Chen