Globalfoundries Inc.

Yiqun Liu

Rohit Pal

Changyong Xiao

Dina H Triyoso

Mitsuhiro Togo

Haiting Wang

Huang Liu

Jin Ping Liu

Sandeep Gaan

Seung Yeon Kim

Shishir K Ray

Wei Hua Tong

Tae-Hoon Kim

Fabio D'Addamio

Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 &#x212b; thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO) and zirconium dioxide (ZrO). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfOand/or tetragonal phase ZrO. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Devices comprising high-K dielectric layer and methods of forming same

A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Threshold voltage control for mixed-type non-planar semiconductor devices

A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Integrated circuits having replacement gate structures and methods for fabricating the same

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Clifton Park, NY, United States of America

Yiqun Liu