Infineon Technologies Ag

Yiqun Cao

Ulrich Glaser

Julien Lebon

Andreas Peter Meiser

Matthias Stecher

Joost Adriaan Willemen

Magnus-Maria Hell

Michael Mayerhofer

Andreas Rupp

Kai Esmark

Herbert Gietler

Donald Dibra

A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element.

Transient voltage protection circuits, devices, and methods

An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a second terminal and being operable at voltage differences between the first terminal and second terminal of greater than +10 V and less than &#x2212;10 V. The integrated circuit additionally includes an ESD protection structure operable to protect the circuit section against electrostatic discharge between the first terminal and the second terminal. The ESD protection structure is operable with voltage differences between the first and second terminals of greater than +10 V and less than &#x2212;10 V without triggering. The ESD protection structure is electrically and optically coupled to a photon source such that photons emitted by the photon source upon ESD pulse loading are absorbable in the ESD protection structure and an avalanche breakdown is initiatable by electron-hole pairs generated by the absorbed photons.

Integrated circuit having an ESD protection structure and photon source

An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.

Integrated circuit including lateral insulated gate field effect transistor

An apparatus and a method for generating signals for ESD stress testing an electronic device are disclosed. In an embodiment the apparatus is configured to receive a source signal including a source pulse, delay the source pulse to generate a test signal including a test pulse with a pulse width in an ESD time range and generate an auxiliary signal including an auxiliary pulse with a pulse width in the ESD time range.

Apparatus and method for generating signals for ESD stress testing an electronic device and system for performing an ESD stress test of an electronic device

A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

Method of triggering avalanche breakdown in a semiconductor device

A circuit is described comprising electrostatic discharge (ESD) protection circuitry, keep-off circuitry and ESD detection circuitry. When the ESD detection circuitry detects an ESD event, the ESD detection circuitry is configured to both enable the ESD protection circuitry and disable the keep-off circuitry.

Noise-tolerant active clamp with ESD protection capability in power up mode

A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.

Semiconductor component and method of triggering avalanche breakdown

A combined electro static discharge clamp for cascaded voltage pins can include an electronic switch, a plurality of discharge paths, and a plurality of trigger circuits. In response to detecting a voltage event across any two voltage pins, the trigger circuitry can turn on the electronic switch causing current caused by the voltage event to flow through one or more of the discharge paths instead of through functional circuitry which could potentially be damaged by the current caused by the voltage event.

Combined ESD active clamp for cascaded voltage pins

A protection circuit includes a controllable discharge element having a load path coupled between a first second circuit nodes. The discharge element provides a discharge path between the first and the second circuit nodes when in an on state. A trigger circuit has a first connection coupled to the first circuit node and a second connections coupled to the second circuit node. The trigger circuit is configured to produce a drive signal that switches the discharge element to its on state when the voltage between the first and the second circuit nodes reaches a trigger value. A setting circuit coupled to the trigger circuit is configured to change the trigger value from a first trigger value to a second trigger value depending on a voltage between the first and the second circuit nodes and/or on the drive signal.

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Munich, Germany

Yiqun Cao