Texas Instruments Corporation

Yiqi Tang

Rajen Manicon Murugan

Liang Wan

Jie Chen

Makarand Ramkrishna Kulkarni

Sylvester Ankamah-Kusi

Li Jiang

Jonathan Almeria Noquil

Enis Tuncer

Usman Mahmood Chaudhry

Guangxu Li

Sreenivasan Kalyani Koduri

Juan Alejandro Herbsommer

Osvaldo Jorge Lopez

Christopher Daniel Manack

John Paul Tellkamp

Satyendra Singh Chauhan

Michael G Amaro

Tony Ray Larson

William Todd Harrison

Hiep Xuan Nguyen

Manu Joseph Prakuzhy

Vivek Swaminathan Sridharan

Naweed Anjum

Ming Li

Steven Alfred Kummerl

Siraj Akhtar

Matthew David Romig

Tianyi Luo

Chittranjan Mohan Gupta

Robert J Falcone

Phuong Minh Vu

A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.

Back end of line structure for improved current density in HR devices

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

Multi-layer semiconductor package with stacked passive components

An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.

Electronic device and multilevel package substrate with integrated filter

A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.

Semiconductor device with multiple dies

An electronic device includes a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

Flip-chip enhanced quad flat no-lead electronic device with conductor backed coplanar waveguide transmission line feed in multilevel package substrate

A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

Multilayer package substrate with stress buffer

A described example includes an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.

Microelectronic device package including antenna and semiconductor device

In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

Plated metal layer in power packages

An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

Electronic device multilevel package substrate for improved electromigration performance

An electronic device with a multilevel package substrate having multiple levels including a first level having conductive leads and a final level having conductive landing areas along a side, as well as a die mounted to the multilevel package substrate and having conductive terminals electrically coupled to respective ones of the conductive leads, and a package structure that encloses the die and a portion of the multilevel package substrate, where the multilevel package substrate has a conductive elevated trace layer with a confinement feature that extends outward from the side of the final level along a third direction that is orthogonal to the first and second directions, the confinement feature having a sidewall configured to laterally confine one of a solder, an adhesive, a side of a passive component, and a side of the die.

Electronic device and multilevel package substrate with elevated trace features for solder and/or die confinement and method for fabricating the electronic device

An electronic device includes a rectangular ceramic package structure having opposite first and second sides, an interior cavity that extends to an opening in the second side, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, and non-conductive indents extending into the third and fourth sides. The device also includes a semiconductor die in the cavity, a lid that covers the opening and seals the cavity, a conductive terminal having a planar side exposed along the first side that is electrically coupled to a circuit of the semiconductor die and extends to a first one of the non-conductive indents, and conductive pins spaced apart from the conductive terminal and extending outward from the first side of the ceramic package structure along a third direction.

Hybrid chip carrier package

Described examples include a method having steps of laying out at least two conductors and modeling conductor current through the at least two conductors to determine a current density in the at least two conductors. The method also has steps of revising the at least two conductors as adjusted conductors to add conductive material to areas of the conductor where the modeling conductor current shows above average current density; fabricating the adjusted conductors; and mounting a die to the adjusted conductors.

Multilayer package substrate with improved current density distribution

An antenna in package (AIP)includes an IC dieincluding bond padsand a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layerincluding a top dielectric layer, a top metal layerincluding an antenna, and a bottom layerincluding a bottom dielectricand a bottom metal layerincluding contact pads including a first contact pad, and filled vias. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillarare electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

Antenna in package having antenna on package substrate

One example includes an antenna-on-package system that includes a multi-layer antenna structure. The antenna structure includes a first conductive layer having a patch antenna and a transmission line. The transmission line extends from a feed-side edge of the patch antenna to terminate in a launch structure. The antenna structure also includes a second conductive layer having a ground reflector spaced apart from the first conductive layer by a layer of dielectric material. An integrated circuit (IC) die has a signal terminal on surface of the IC die, and a conductive signal interconnect extends through the layer of dielectric material and is coupled between the signal terminal and the launch structure.

Antenna-on-package system

A semiconductor device includes a die with a power converter module. The power converter module includes an output port and a return port. The semiconductor device also includes a connection assembly that includes pads configured to be coupled to circuit components of a printed circuit board (PCB). The connection assembly also includes a first layer patterned to include a first trace that is coupled to one of the output port and the return port and a second trace that is coupled to the other of the output port and return port. A second layer of the connection assembly is patterned to provide a first via between the first trace and a third layer and a second via between the first trace and the third layer. The third layer is patterned to provide a portion of a first conductive path and a portion of a second conductive path.

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Allen, TX, United States of America

Yiqi Tang