Uniband Electronic Corp.

Koninklijke Philips Corporation N.v.

Mediatek Corporation

Mediatek USA Inc.

Hyperband Communication, Inc.

Hyperband Communications, Inc.

Yiping Fan

Chieh-Yuan Chao

Hongyu Li

Li-Feng Chen

Syang-Myau Hwang

Kanyu Cao

Chun-Chin Chen

Sifen Luo

Chen-Yi Chang

Chun-Yuan Lin

Sheng-Chia Huang

Sheng-Wei Chiang

A radio frequency (RF) receiver has an antenna, a low-noise amplifier, a sigma-delta frequency synthesizer/voltage-controlled oscillator (VCO), an in-phase and quadrature (I/Q) mixer, a channel filter, and a digital baseband circuit. The digital baseband circuit has a demodulator, a preamble detection and carrier frequency offset (CFO) estimation circuit, and a CFO to sigma-delta modulation (SDM) input mapper. A preamble field of a digital demodulated signal generated by the demodulator is detected by the preamble detection and CFO estimation circuit. The RF receiver simultaneously compensates its CFO and optimizes a bandwidth of the channel filter based on the detection of the preamble field of the digital demodulated signal by the preamble detection and CFO estimation circuit.

RF receiver and method for simultaneously compensating carrier frequency offset and optimizing bandwidth by using preamble of a received RF signal

A signal receiver includes a multiplexer, a sub-sample analog-to-digital converter (ADC) and a received signal strength indicator (RSSI) estimator for a signal receiver with multiple stage cascade amplifiers architecture. The multiplexer may select one of the input signal of each stage of cascade amplifiers or the last stage output signal of cascade amplifiers as a selected signal according to a selection signal. The sub-sample ADC may perform a sub-sampling operation using the selected signal to generate sampled data. The RSSI estimator may calculate a RSSI value corresponding to the selected signal according to the sampled data.

Signal receiver for radio signal strength indication estimation with sub-sampling analog-to-digital converter for radio frequency signal with constant envelope modulation

A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold.

Digital receiver system activated by RSSI signal

An IEEE 802.15.4 DSSS Offset-QPSK device is proposed that allows an existing system to transfer Offset-QPSK modulation signal into MSK modulation signal, then deliver the MSK modulation signal without DSSS to increase payload data transmission rate. On-the-fly detection of whether a low data rate or a high data rate encoding mode is used for a received frame is attained by the transmitter setting a predetermined bit in the frame length byte of a transmitting frame. Thus an extra high data rate transmission for IEEE 802.15.4 DSSS Offset-QPSK systems can be provided.

Multi-rate coexistence scheme in DSSS O-QPSK network

A transceiving system utilizing a shared filter module is provided. The shared filter module is selectively filtering signals in a first band in a first mode and a second band in a second mode. The first mode is a receiver mode whereas the second mode is a transmission mode. The shared filter module comprises a compound filter comprising two low pass filters and a coupling controller to manage input and output wiring of the low pass filters. When the coupling controller is enabled in the first mode, the compound filter acts as a bandpass filter. When the coupling controller is disabled, the compound filter acts as two independent low pass filters.

Transceiving system and compound filter

A spread spectrum receiver whose de-spreading process based on transformed spreading codes is provided. Instead of de-spreading with original spreading codes, this approach de-spreads received signal with the spreading codes transformed from the original codes in order to eliminate the negative impact of system impairments such as frequency offset to a spread spectrum receiver. Before de-spreading with the transformed code, the received signal goes through the same transformation as the original codes do. After a transformation, the transformed codes may exist some undesirable property such as spreading code having DC content. An approach is given to cancel unwanted side effects relating the transformed spreading codes. The approaches are very effective for spread spectrum system based on frequency modulation scheme such as MSK. For this kind of system, the frequency offset translates to DC offset after the transformation and the DC offset can be cancel since the DC property of the transformed spreading code is known in advance.

Receiver based method for de-spreading of spread spectrum signal

Fast settling circuits and methods designed to align input signal amplitude level and to remove DC offset voltages with minimal loss of low frequency signal in receiving analog circuits are disclosed. With the key innovative circuits and methods for signal peak alignment, the disclosed circuits and methods achieve fast settling without significant attenuation of the input signal. Peak aligning circuits and methods can be implemented along with conventional RC AC coupling circuits. In applying the aligning circuits and methods to differential signal pair, DC offsets can be easily removed.

Circuits and methods for fast-settling signal alignment and DC offset removal

In a spread spectrum system, methods and despreader architectures for despreading the received spreaded codes with the use of a single correlator and a single correlation code is provided. Before despreading the incoming received spreaded codes, a single correlation code is generated using a symbol from a set of symbols that has been mapped into a set of differential encoded PN codes. Despreading output samples for each received spreaded code are obtained by correlating the received spreaded code with this single correlation code. Correlation is accomplished by multiplying each received sample of the received spreaded codes with the correlation code samples and accumulating the products of this multiplication. After correlation, the index for the maximum or minimum peak of the despreading output samples for each code is identified. This index can then be mapped into a symbol corresponding to the transmitted information. Corresponding despreader architectures comprise of a number of taps attached to a series of shift registers. Received samples of each received spreaded codes are inputted into the shift registers. The despreader architectures accumulates the products of multiplication of the value of the shift register with a predetermined value associated with each tap to produce the despreading output samples of a received spreaded code. It identifies the despreading output index producing the maximum of the absolute value of the despreading output and maps said index into a symbol corresponding to the transmitted information.

Chip-to-symbol receiver despreader architectures and methods for despreading spread spectrum signals

The present invention provides methods and apparatuses for an amplifier circuit for amplifying an input signal. An amplifier circuit for amplifying an input signal comprises an amplifying transistor circuit having a power transistor and a dc bias circuit having a plurality of current mirror circuits and a discharge transistor wherein the discharge transistor and the power transistor form a combined current mirror circuit to control quiescent current in the power transistor.

RF amplifier with a bias boosting scheme

The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential output in response to the first and second differential signals and the third and fourth cascoded differential amplifiers are configured to provide a second differential output in response to the first and second differential signals.

Active polyphase filter

A phase-locked loop fractional-N frequency synthesizer, particularly of a sigma delta type, has a voltage controlled oscillator, a fractional-N frequency divider, a phase comparator, a charge pump, and a loop filter. The loop filter has a capacitive element for receiving a charge pump current from the charge pump. A filtered charge pump current controls the voltage controlled oscillator. The charge pump is operable in three current modes, a pre-charging/pre-discharging mode, a speed up mode, and a normal, locked mode. In the pre-charging/pre-discharging mode the charge pump is decoupled from the phase comparator so that the phase locked loop is open, and in the speed up and normal modes the charge pump is coupled to the phase comparator so that the phase locked-loop is closed.

Frequency synthesizer with three mode loop filter charging

A frequency synthesizer is provided that allows for a half-cycle division of the synthesized frequency. In a conventional sigma-delta fractional-N frequency synthesizer, a controllable divider is configured to allow for the division of the synthesized frequency by an integer factor of N or an integer factor of N&plus;1. A sigma-delta calculator controls a half-cycle divider so as to selectively divide the synthesized frequency by an integer factor of N, or a fractional factor of (N&plus;&frac12;). If a higher order sigma-delta calculator is employed that provides S output symbols, the half-cycle divider is correspondingly controlled to select a division factor of (N&plus;s/2), where s is selectable from set of S symbols.

Sigma delta fractional-N frequency divider with improved noise and spur performance

A decimator is provided that selectively varies the output sampling rate of an integer decimating device, such that the average output sampling rate corresponds to a desired output sampling rate. The output sampling rate varies such that an output sample is provided selectively after N input samples, or after N&plus;1 input samples, to provide an output-to-input sampling ratio that is between N and N&plus;1. This process introduces phase jitter as the sampling frequency varies between 1/N and 1/(N&plus;1), but if the oversampling rate is high, and therefore N is high, as is typical of many applications that employ oversampling, the relative magnitude of the phase jitter is slight. A fractional accumulator is used to control whether the output occurs after N or N&plus;1 input cycles, and is clocked by the input sampling clock, thereby minimizing the complexity of the embodiment.

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Fremont, CA, United States of America

Yiping Fan