Ol Security Limited Liability Company

Calos Fund Limited Liability Company

Polycom, Inc.

Ol Security Limited Liability

Yipeng Liu

Ujval J Kapasi

Dan Miller

Amit Gulati

John Seivers

Edmund S Thompson

John C Sievers

John Sievers

Instructions embedded on a computer-readable medium, when executed on one or more computer devices, improve video coding performance while using a merge mode in motion estimation. The instructions comprise instructions to perform one or more refinement searches on a plurality of candidate regions of a current frame. The instructions also comprise instructions to determine one or more distortion values based, at least in part, on reduced candidate regions and instructions to code motion data based, at least in part, on the one or more refinement searches.

Hierarchical packing of syntax elements

A method operates within an integrated circuit having a plurality of processing lanes. For each of a first and second processing lanes, the method determines a number of packed data words among one or more packed data words associated with the respective processing lane, associates the number of packed data words with a used field of the processing lane, wherein the used field indicates the number of packed data words in the processing lane; and stores the one or more packed data words in a variable record length memory based, at least in part, on the used field of the processing lane.

A method operates within an integrated circuit device having a plurality of processing lanes. The method determines a first number of packs among one or more first packs associated with a first processing lane of the plurality of processing lanes, associates the first number of packs with a first used field of the first processing lane, determines a second number of packs among one or more second packs associated with a second processing lane of the plurality of processing lanes, and associates the second number of packs with a second used field of the second processing lane.

A method of operation within an integrated circuit device having a plurality of processing lanes. A first sub-stream of data, having a variable length, is generated in a first one of the processing lanes. A second sub-stream of data, also having a variable length, is generated in a second one of the processing lanes. The first and second sub-streams are then output to form a single bitstream.

A method of encoding a block of data. A first plurality of data in the block of data is assigned a worth based on a first algorithm. A second plurality of data, which is lower in frequency than the first plurality of data, in the block of data is assigned a worth according to a second algorithm. The block of data is assigned a worth based on the worth of the first plurality of data and the second plurality of data. The worth of the block of data is then compared to a threshold value, and subsequently one or more data values of the block of data are adjusted based on the comparison.

Fast detection and coding of data blocks

The error concealment technique disclosed herein relates to the use of existing information by the decoder to conceal bitstream errors regardless of what the encoder does. Examples of existing information include, for example, the previous reference frame, macroblock information for the previous reference frames, etc. Another aspect of the system described herein relates to the steps that the encoder can take to enhance the decoder's ability to recover gracefully from a transmission error. Exemplary steps that can be taken by the encoder include intra walk around and sending GOB headers. Although these encoder techniques can provide greatly enhanced results, they are not strictly necessary to the system described herein.

Growing community of inventors

Sunnyvale, CA, United States of America

Yipeng Liu