Sony Semiconductor Solutions Corporation

Yinta Lin

Yoshinori Takahashi

Sho Ohashi

Riichi Nishino

Hideo Yamaji

In a circuit provided with a phase comparator, a lock time is shortened. The phase comparator compares between a phase of a reference clock signal that has been input and a phase of a feedback clock signal, and outputs a comparison result. A charge pump generates a control voltage for control of a frequency of the feedback clock signal on the basis of the comparison result. A feedback unit generates the feedback clock signal in response to the control voltage. A stop detection unit detects whether or not the reference clock signal is stopped, and initializes the comparison result in a case where the reference clock signal is stopped.

Semiconductor integrated circuit, electronic device, and control method for semiconductor integrated circuit

A phase locked loop of the present disclosure includes a phase comparator circuit, a loop filter, an oscillator circuit, an AD converter circuit, and a current generator circuit. The phase comparator circuit compares a phase of a first signal and a phase of a second signal based on a clock signal. The loop filter includes a resistor element and a capacitor element, and generates a control voltage on the basis of a phase comparison result of the phase comparator circuit. The resistor element has one end coupled to a first node and another end coupled to a second node. The capacitor element has one end coupled to the second node. The oscillator circuit generates the clock signal on the basis of the control voltage. The AD converter circuit converts a voltage difference between the two ends of the resistor element into a digital code. The current generator circuit generates a first current on the basis of the digital code and supplies the first current to the second node.

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Tokyo, Japan

Yinta Lin