Zte Corporation

Yingxin Wang

Bi Yi

Yonghui Ren

Changgang Yin

Fengchao Ma

Xinjian Chen

Wang Xiong

Rongxing Ban

Huazhang Cao

Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (), which includes a first board () and a second board (), and is connected to a testing device; and a second PCB (), which includes a third board () and a fourth board (), and is connected to the testing device. The first board () is connected to the third board () through a connector ().

Connector structure, and skew calculation method and device

Provided are a circuit board, an apparatus and a method for forming a via hole structure. A via hole structure formed on a main body () of a circuit board includes a hole () enclosed by a conductive layer in the main body (), the conductive layer constitutes a wall () of the hole (), and a dielectric filling layer (), which has a dielectric constant smaller than that of the main body (), is disposed between at least a portion of the wall () of the hole () and the main body (), so that the parasitic capacitance of a via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving impedance continuity of a system link.

Circuit board, apparatus and method for forming via hole structure

The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

PCB processing method and PCB

Growing community of inventors

Guangdong, China

Yingxin Wang