Link a Media Devices Corporation

Sk Hynix Memory Solutions Inc.

Tidal Systems, Inc.

Micron Technology Incorporated

Beijing Tenafe Electronic Technology Co., Ltd.

Seagate Technology Incorporated

Other

Beijing Tenate Electronic Technology Co., Ltd.

Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Tenafe, Inc.

Yingquan Wu

Alexander Hubris

Meng-Kun Lee

Marcus Marrow

Eyal En Gad

Erich Franz Haratsch

Earl T Cohen

Zhengang Chen

Sundararajan Sankaranarayanan

AbdelHakim S Alhussien

Yunxiang Wu

Abdelhakim Alhussien

Yu Kou

Ning Chen

Kwok Wah Yeung

Xiangyu Tang

Nishant P Patil

Ivana Djurdjevic

Gregory Lee Silvus

Thomas V Souvignier

Kwok Alfred Yeung

Armin Banaei

Xiaojie Zhang

A level count disparity is determined based at least in part on: (1) an expected count of a plurality of cells in solid state storage and (2) an observed count of the plurality of cells in the solid state storage, where the observed count is associated with a number of cells in the solid state storage that are activated by performing a single read on the solid state storage using a previous read threshold. A next read threshold is determined, including by: determining a direction relative to the previous read threshold based at least in part on the level count disparity and independent of the second and earlier level count disparity; and determining a magnitude based at least in part on the level count disparity and the second and earlier level count disparity. Read data is obtained using the next read threshold and error correction decoding is performed.

Adaptive DSP generation of read thresholds for gaussian and non-gaussian distributions in solid state storage using cumulative observed counts

An input sequence that has a plurality of bits is received where the input sequence is associated with a first section of data within a compressed block. The plurality of bits in the input sequence are divided into a first sub-sequence comprising a first set of bits and a second sub-sequence comprising a second set of bits. The first sub-sequence is encoded using a first Huffman code tree to obtain a first codeword and the second sub-sequence is encoded using a second Huffman code tree to obtain a second codeword. Encoded data that includes information associated with the first Huffman code tree, information associated with the second Huffman code tree, the first codeword, and the second codeword is output.

Deflate compression using sub-literals for reduced complexity Huffman coding

Low-density parity-check (LDPC) encoded data with one or more errors is received. Information associated with an early convergence checkpoint that occurs at a fractional iteration count that is strictly greater than 0 and strictly less than 1 is received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. At the early convergence checkpoint that occurs at the fractional iteration count, it is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Early convergence for decoding of LDPC codes

Read data associated with Flash storage that is in a Flash storage state is received. One of a plurality of log-likelihood ratio (LLR) mapping tables is selected based at least in part on: (1) the Flash storage state and (2) a decoding attempt count associated with a finite-precision low-density parity-check (LDPC) decoder. A set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as the finite-precision LDPC decoder. The finite-precision LDPC decoder generates the error-corrected read data using the set of LLR values and outputs it.

Log-likelihood ratio mapping tables in flash storage systems

An example methods for interleaved BCH codes can include encoding a plurality of portions of data using a first generator polynomial to obtain a plurality of respective BCH codewords. The method can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The method can include outputting the plurality of respective BCH codewords and the additional BCH codeword.

Apparatuses and methods for interleaved BCH codes

Partition information associated with one or more partitions that divide a range of values into at least a higher and lower set of values is received. An uncompressed value that falls within the range of values is received and a compressed value that includes a set indicator and intra-set information is generated using the uncompressed value. This includes generating the set indicator based at least in part on whether the uncompressed value falls in the higher or lower set of values, determining whether the uncompressed value includes an extraneous bit where it is necessary but not sufficient that the uncompressed value fall in the higher set of values for the uncompressed value to include the extraneous bit, and generating the intra-set information, including by: excluding the extraneous bit in the uncompressed value from the intra-set information if it is determined to be included. The compressed value is output.

Data compression techniques using partitions and extraneous bit elimination

A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.

Performing a decoding operation to simulate switching a bit of an identified set of bits of a data block

A literal element that has a plurality of bits is received. The plurality of bits in the literal element is divided into a first sub-literal comprising a first set of bits and a second sub-literal comprising a second set of bits. The first sub-literal is encoded using a first Huffman code tree to obtain a first sub-literal codeword; the second sub-literal is encoded using a second Huffman code tree to obtain a second sub-literal codeword. Encoded data that includes information associated with the first Huffman code tree, information associated with the second Huffman code tree, the first sub-literal codeword, and the second sub-literal codeword is output.

A level count disparity is determined based at least in part on an expected count of a plurality of cells in a solid state storage and an observed count of the plurality of cells in the solid state storage, where the observed count is obtained from a read performed on the solid state storage using a previous read threshold. A next read threshold is determined based at least in part on the level count disparity. A read is performed on the solid state storage using the next read threshold to obtain read data and error correction decoding is performed on the read data.

Read data associated with Flash storage is received. One of a plurality of LLR mapping tables is selected and a set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as a finite-precision low-density parity-check (LDPC) decoder. Error-corrected read data is generated using the set of LLR values, where the finite-precision LDPC decoder has the same finite precision as the set of LLR values. The error-corrected read data is output.

A saturation metric that represents a degree of saturation in a low-density parity-check (LDPC) decoding system that uses a fixed-point number representation is determined. The saturation metric is compared against a saturation threshold. In the event the saturation metric exceeds the saturation threshold, at the end of a decoding iteration, a message is more aggressively attenuated compared to when the saturation metric does not exceed the saturation threshold in order to produce an attenuated message. In the event the saturation metric does not exceed the saturation threshold, at the end of the decoding iteration, the message is less aggressively attenuated compared to when the saturation metric does exceed the saturation threshold in order to produce the attenuated message.

Low-density parity-check decoding with desaturation

Low-density parity-check (LDPC) encoded data with one or more errors and information associated with an early convergence checkpoint are received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword where the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. It is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Partition information associated with partition(s) in a sliding window and an uncompressed value associated with a repeated sequence in the sliding window are received. A compressed value is generated using the uncompressed value, including by: generating the set indicator based at least in part on the partition information and the uncompressed value; determining, based at least in part on the partition information and the uncompressed value, whether the uncompressed value includes an extraneous bit; and generating the intra-set information, including by: in the event it is determined that the uncompressed value includes the extraneous bit, excluding the extraneous bit in the uncompressed value from the intra-set information. The compressed value is output.

A set of bits of a data block that is associated with an unsuccessful first decoding operation may be identified. A second decoding operation to simulate switching at least one bit of the set of bits may be performed. At least one bit of the set of bits switched during the performance of the second decoding operation may be determined to correspond to an error. The error from the at least one bit of the set of bits may be corrected by changing a value of the at least one bit.

A dynamic dictionary-based data symbol encoder. A dynamic dictionary data structure is populated with evictable dictionary entries. The evictable dictionary entries are encoded with a dictionary index that is shorter than an original representation of the input symbols. A reference count evicts dictionary indices when eligible for eviction. Through building a dynamic symbol dictionary which is much smaller than (global) alphabet size, locally repetitive symbols can be effectively compressed using dictionary. The dictionary is also dynamically built along with the compression/decompression process and therefore does not carry overhead. However, tables/trees might be appended to enable entropy decoding. The method is also readily combined with the popular LZ77 and its variant encoding methods into composite one-pass encoding algorithms to achieve superior performance.

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Yingquan Wu