Reed Semiconductor Corp.

Yingqian Ma

Jiwei Fan

Jialun Du

Hal Chen

Jingyuan Chen

Yifan Dong

Wenkai Wu

Weidong Zhu

Qian Chen

Cheng-Wei Chen

An apparatus includes a plurality of switches connected in parallel between an input terminal and an output terminal of a power bus, a plurality of current sensing circuits coupled to the plurality of switches, wherein each current sensing circuit is coupled to a corresponding switch, and a plurality of current sharing circuits configured to receive current sensing signals from the plurality of current sensing circuits and generate a plurality of gate drive signals to control the plurality of switches so as to achieve a predetermined current distribution among the plurality of switches.

Current sharing apparatus and control method

A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.

Frequency lock loop for constant switching frequency of DC-DC converters

A ramp generator for and method of generating a voltage ramp signal with very long ramping up time on a silicon chip, wherein the method includes a control loop providing a switched-capacitor circuit for generating the voltage ramp signal.

Internal ramp voltage generator for the soft start of DC-DC converter

A ripple amplitude compensation circuit for ripple-based control of DC-DC converter, wherein the ripple amplitude compensation circuit for adjusts the gains of the voltage loop and ripple loop according to the ripple amplitude. With the present invention, the ripple-based control loop's performance can be optimized.

Ripple amplitude compensation circuit for ripple based control of DC-DC converter

A ramp generator for a constant on-time DC-DC converter, wherein the ramp generator is configured to reduce DC offset and smooth transitions between conduction modes. The ramp voltage generator includes a common voltage generator suitable for generating a common voltage; a first ramp voltage generation block suitable for generating a first ramp voltage responsive to a first switching signal and a control signal, wherein the first switching signal resets one or more valley points of the first ramp voltage to one or more valley points of the common voltage; and a second ramp voltage generation block suitable for generating a second ramp voltage responsive to a second switching signal, the first ramp voltage, and the control signal.

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Shenzhen, China

Yingqian Ma