Boe Technology Group Co., Ltd.

Beijing Boe Display Technology Co., Ltd.

Hefei Xinsheng Optoelectronics Technology Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Yingmeng Miao

Yanping Liao

Zhihua Sun

Xibin Shao

Dongchuan Chen

Seungmin Lee

Qiujie Su

Feng Qu

Jiantao Liu

Shulin Yao

Chongyang Zhao

Cong Wang

Yinlong Zhang

Tao Yang

Xiaofeng Yin

Wenjie Hou

Zheng Zhang

Haipeng Yang

Yingying Qu

Maoxiu Zhou

Wenpeng Ma

Pengfei Hu

Changcheng Liu

Lei Guo

Ke Dai

Yue Yang

Zhangtao Wang

Yujie Gao

Bo Hu

Yuntian Zhang

Jianhua Huang

Xiaochun Xu

Panhui Zhao

Yuhang Tian

Wei Zhang

Peng Hui Jiang

Xu Zhang

Guangliang Shang

Xin Zhou

Haoliang Zheng

Xing Yao

Seungwoo Han

Li Tian

Dong Hui Liu

Yan Yan

Mingfu Han

Yuanbo Zhang

Ting Dong

Wenkai Mu

Guohuo Su

Yifu Chen

Zhihao Zhang

Baoyu Liu

Xipeng Wang

Benzhi Xu

Weichao Ma

Lingdan Bo

Senwang Li

Zhihe Jin

Guangquan He

Yinshu Zhang

Changchen Liu

Dong Liu

The embodiments of the present disclosure provide a drive control circuit, a control method thereof, and a display apparatus. The drive control circuit includes: a first control circuit configured to acquire image data, and output a first selection command signal according to the image data; and at least one second control circuit each coupled to at least one scan signal line in a display panel and coupled to the first control circuit. The at least one second control circuit is configured to receive the first selection command signal, determine, according to the first selection command signal, a target scan signal line from among scan signal lines in the display panel, and output a scan drive signal to the target scan signal line.

Drive control circuit, control method thereof, and display apparatus

The method includes, during a data refresh stage of at least one display frame, loading a gate turn-on voltage to a gate line, and loading, on each data line, a data voltage of an image to be displayed, so that each sub-pixel inputs a corresponding data voltage, and during a blanking time period, loading a gate turn-off voltage to a gate line, and loading a compensation voltage to each data line. When a data voltage in a sub-pixel connected to a data line is greater than a common electrode voltage, a compensation voltage is less than the data voltage in the sub-pixel connected to the data line, and/or when the data voltage in the sub-pixel is less than the common electrode voltage, the compensation voltage is greater than the data voltage in the sub-pixel.

Method for driving display panel that during a blanking time phase loads a compensation voltage to each data line, display drive circuit, and display device

There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.

Gate driving circuit and driving method thereof and display panel

A display apparatus includes sub-pixels, at least one gate line group and a scan drive circuit. The gate line group includes a first gate line, a second gate line and a third gate line. The scan drive circuit outputs, in a frame scan cycle, a first scan signal to the first gate line, a second scan signal to the second gate line, and a third scan signal to the third gate line in sequence. Durations of effective scan periods of the scan signals are equal. A start moment of the effective scan period of the second scan signal is delayed by a first time length compared with that of the first scan signal. A start moment of the effective scan period of the third scan signal is delayed by a second time length less than the first time length compared with that of the second scan signal.

Display apparatus and driving method therefor

The present disclosure provides a display panel driving method, a display panel and a display device, the method comprising: comprising alternately configure display time periods and touch time periods in one time frame, at least one touch time period being configured, and at least two display time periods being configured; sequentially scanning in each display time period a portion of gate lines in a display panel; and pausing in each touch time period the scanning of all gate lines, and performing touch recognition, wherein in a display time period adjacent to a touch time period, level compensation is performed on a gate line to be compensated, and the gate line to be compensated is at least one gate line that starts to scan in the display time period adjacent to the touch time period.

Driving method for display panel, display panel, and display device configured with time frame comprising at least two display time periods and at least one touch time period which are alternately configured

An array substrate includes a gate drive circuit including shift register units in cascade. The driving method includes: in a first driving mode, loading a first clock signal with an active level and an inactive level alternating periodically to a cascade clock signal terminal of a shift register unit, and loading a second clock signal with an active level and an inactive level alternating periodically to any one of K drive clock signal terminals of the shift register unit; and in a second driving mode, loading the first clock signal to the cascade clock signal terminal, and loading a third clock signal with an active level appearing within a target time period to a target drive clock signal terminal among the K drive clock signal terminals so that a target drive output terminal corresponding to the target drive clock signal terminal outputs a gate turn-on signal.

Array substrate including gate drive circuit with shift register units in cascade, display device and driving method

Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a plurality of data lines and sub-pixels. At least one sub-pixel includes: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.

Array substrate and manufacturing method thereof, and display device

A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level conversion unit and a gate electrode driving unit; and the gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals in response to a first portion of the plurality of first output signals received at a first moment by a first portion of the plurality of second clock signal input terminals, and sequentially output a plurality of second gate scan signals by a second portion of the 2n gate signal output terminals in response to a second portion of the plurality of first output signals received at a second moment by a second portion of the plurality of second clock signal input terminals.

Driving circuit, display device, and driving method

A driving method for a display panel and a display apparatus. The driving method includes: acquiring display data of a to-be-displayed image in a current display frame (S); and loading a data voltage on a data line in the display panel according to the display data, such that each sub-pixel in the display panel is charged with the corresponding data voltage (S).

Display panel having different voltage conversion edge for positive and negative data voltages and driving method thereof

An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.

Array substrate and display panel

A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.

Display panel, driving method for the display panel and display device

A display substrate, including: a base substrate; a plurality of data lines on the base substrate; a first insulating layer on a side of the plurality of data lines away from the base substrate; a plurality of gate lines on a side of the first insulating layer away from the plurality of data lines, where extension directions of the gate and data lines are intersected; a second insulating layer on a side of the plurality of gate lines away from the first insulating layer; and a first electrode on a side of the second insulating layer away from the plurality of gate lines, where at least a portion of an orthographic projection of the first electrode on the base substrate is within an region surrounded by orthographic projections of two adjacent data lines on the base substrate and orthographic projections of two adjacent gate lines on the base substrate.

Display substrate, display panel and display device

A driving method for a display panel and a display apparatus. The driving method includes: obtaining original display data of a current display frame; and when it is determined to adopt a first driving mode, loading first gate scanning signals (GA_-GA_) to gate lines (GA, GA-GA) in the display panel, and loading a data voltage to data lines (DA, DA-DA) in the display panel according to target display data obtained by removing a part of data from the original display data, so as to charge each sub-pixel in the display panel with the data voltage.

Driving method for display panel including sub-pixel rows divided into sub-pixel row groups and display apparatus including display panel

At least one chip group and a group of first PLG wirings corresponding to each of the chip groups are disposed in a first bonding area, each of the chip groups includes at least two groups of chip units, each group of the chip units includes at least one gate drive chip, each group of the first PLG wirings includes a first wiring and at least one second wiring; power pins of any two adjacent gate drive chips are connected by the first wiring, each of the second wirings surrounds and passes through each of the gate drive chips, the first wirings connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings, are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units.

Display module having low difference in pixel luminance and display apparatus

The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display apparatus. The array substrate has a display area and a peripheral wiring area provided at at least one side of the display area. The display area includes a thin film transistor and a common electrode formed on the base substrate; the peripheral wiring area includes a first lead, a gate signal line and a common signal line formed on the base substrate; the first lead and the gate electrode of the thin film transistor are arranged in an identical layer and are electrically connected; the gate signal line is located on a side of the first lead away from the base substrate, and is electrically connected to the first lead through a first transition structure.

Array substrate and display apparatus

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Beijing, China

Yingmeng Miao