Texas Instruments Corporation

Infineon Technologies Canada Inc.

Yinglai Xia

Yogesh Kumar Ramadass

Shailendra Kumar Baranwal

Junmin Jiang

Nan Xing

Edward MacRobbie

Yalong Li

Robert Wayne Mounger

Zhemin Zhang

Lucas Andrew Milner

Sridhar Ramaswamy

Krishnaswamy Nagaraj

Jessica Danielle Boles

Bhushan Talele

Arvind Sivakumar

A power transistor current sense circuit. The control nodes of each of a power transistor and sense transistors are connected. The input nodes of the power transistor and each of the sense transistors are also connected. A voltage divider is connected between a reference voltage source and the output node of a second sense transistor. A negative feedback circuit is connected between the output of the voltage divider and the output node of the first sense transistor. The negative feedback circuit forces a voltage at the output node of the first sense transistor to be approximately equal to the divided voltage. A power transistor current determination component measures a sense current that passes through the first sense transistor, and from that detects the current passing through the power transistor.

Power current signal generation using sense transistors

A circuit that includes a power transistor and at least one sense transistor and that uses the control drive terminal to not only control the power transistor and the sense transistor, but also to provide power to a current sense circuit. The control nodes of the power transistor and sense transistor are connected, and the input nodes of the power transistor and the sense transistor are also connected. The current sense circuit is connected to the sense transistor control node and is configured to detect current passing through the sense transistor. The current sense circuit is also connected to the control drive terminal and is configured to draw power from the control drive terminal when a high control signal is present on the control drive terminal. Accordingly, the current sense circuit does not require an independent fixed high voltage supply in order to operate.

Circuit with power transistor and current sense that uses control drive as power source

A driver circuit for a power transistor. The driver circuit allows for robust turn-off of the power transistor, and for reduced power losses when the power transistor transitions back on. The driver circuit controls what voltage is applied to the gate terminal of the power transistor. The driver circuit prevents unintended turn-on of the power transistor by applying a negative voltage to the gate terminal of the power transistor when transitioning off. The driver circuit allows for reduced power losses when transitioning back on by allowing the gate terminal of the power transistor to increase from the negative voltage to a less negative voltage before applying a positive voltage to turn on the power transistor.

Driver circuit for a power transistor

A system includes a charge pump having an input coupled to a first voltage and an output at a second voltage, the second voltage greater than the first voltage. The system also includes an amplifier having a first input, a second input, and a third input, the first input coupled to the output of the charge pump, the second input coupled to the first voltage, the third input coupled to an input signal, the amplifier having an amplified output signal. The system also includes a maximum power detector coupled to the amplifier, the maximum power detector operable to determine whether the amplified output signal has reached a threshold output level and to reduce a power of the amplified output signal responsive to the determination.

Maximum power detection and automatic gain control for capacitive class-D amplifiers

A power transistor circuit suppling an internal voltage to an internal voltage supply node. The power transistor circuit includes external terminals, to each of which signals and/or voltages are applied, for each of the input node, output node and control node of the power transistor. The power transistor circuit includes the power transistor, a current draw transistor, a first diode connected between an external control terminal and the internal voltage supply node, and a second diode connected between the current draw transistor output node and the internal voltage supply node. The power transistor circuit includes a charge pump that receives power from the internal voltage supply node and outputs a voltage to the control node of the current draw transistor. In operation, the internal voltage supply node receives power from the external control terminal via the first diode, or an external input terminal via the current draw transistor and the second diode.

Power transistor circuit that generates internal voltage supply

Described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. The first mux input is coupled to the differential amplifier output. There is a signal generator having a generator input coupled to the mux output. There is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.

Current limit for charge pump boost driven class D audio amplifier

A switching amplifier includes a first portion of a power stage; a second portion of a power stage; a pulse-width modulation (PWM) control loop coupled to control inputs of the first portion of the power stage; and a linear amplifier coupled to control inputs of the second portion of the power stage. The PWM control loop controls a first switch and a second switch of the first portion of the power stage. Between current terminals of the first switch and the second switch is a first signal output of the switching amplifier. The linear amplifier controls a third switch and a fourth switch of the second portion of the power stage. Between current terminals of the third switch and the fourth switch is a second signal output of the switching amplifier.

Switching amplifier having linear transition totem pole modulation

Methods, apparatus, systems, and articles of manufacture are disclosed to generate a modulation protocol to output audio. An example apparatus includes a modulation circuit including a first input, a second input, a first output, and a second output; a first gate coupled to the first output of the modulation circuit; a second gate coupled to the second output of the modulation circuit; a first multiplexer including a first input coupled to the first output of the modulation circuit, a second input coupled to the output of the second gate, and an output coupled to a first switch; and a second multiplexer including a first input coupled to the second output of the modulation circuit, a second input coupled to the output of the first gate, and an output coupled to a second switch.

Methods and apparatus to generate a modulation protocol to output audio

A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Folded ramp generator

A power converter including a piezoelectric resonator. The power converter includes a first transistor coupled between an input terminal and a first plate of the piezoelectric resonator, and a second transistor coupled between the first plate of the piezoelectric resonator and an output terminal. A load may be coupled at the output terminal. Controller circuitry has inputs coupled to the input node, the output node, and to the first plate of the piezoelectric resonator, and outputs coupled to control terminals of the first and second transistors. The controller circuitry operates to turn on the first transistor responsive to a comparison of voltages at the first plate and the input terminal, turn on the second transistor responsive to a comparison of voltages at the first plate and the output terminal, and turn off one of the first and second transistors responsive to an output level at the output terminal.

Closed loop control for piezoelectric-based power converters

A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180&#xb0; out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.

Ramp generator for multilevel class-D amplifiers

An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.

Growing community of inventors

Plano, TX, United States of America

Yinglai Xia